Buffer circuit using capacitors to control the slow rate of a dr

Details Buffer circuit using capacitors to control the slow rate of a dr Buffer circuit using capacitors to control the slow rate of a dr

1992-11-24

1994-05-31

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307263, H03K 1907, H03K 512

Patent

active

053172060

ABSTRACT:
First and second capacitor circuits responsive to a potential applied to an input node for instantaneously supplying a voltage derived by capacitance division to control electrodes of first and second output MOS transistors which drive an output node. When the output node reaches a predetermined potential level, the control electrode node of the first output transistor or the control electrode node of the second output transistor is driven to ground potential or power supply potential by the MOS transistor responding to a delay signal of an input signal. A smaller buffer circuit which has improved output response and reduced through current is described. The output signal transitioning speed can also be easily altered.

REFERENCES:
patent: 4760279 (1988-07-01), Saito et al.
patent: 4908528 (1990-03-01), Huang
patent: 4973861 (1990-11-01), Difken
patent: 5017807 (1991-05-01), Kriz et al.
patent: 5120992 (1992-06-01), Miller et al.

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