Buffer circuit used in a semiconductor device operating by diffe

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307452, 307469, H03K 19003, H03K 19094, H03K 1920

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active

050971522

ABSTRACT:
In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a normal power supply potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a high potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

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IBM Technical Disclosure Bulletin, vol. 30, No. 7, Dec. 1987, CMOS Output Inverter Circuit with Low Power Test Output Inverter, pp. 54-55.

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