Buffer circuit used in a semiconductor device operating by diffe

Details Buffer circuit used in a semiconductor device operating by diffe Buffer circuit used in a semiconductor device operating by diffe

1989-09-12

1991-03-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307465, 307448, 307443, H03K 190175, H03K 19173, H03K 19094, H03K 19020

Patent

active

050032054

ABSTRACT:
In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a high potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a normal power supply potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

REFERENCES:
patent: 4571509 (1986-02-01), Tobita
patent: 4638187 (1987-01-01), Boler et al.
patent: 4680487 (1987-07-01), Kobayashi
patent: 4779013 (1988-10-01), Tanaka
patent: 4785203 (1988-11-01), Nakamura
patent: 4857770 (1989-08-01), Partovi et al.
patent: 4882507 (1989-11-01), Tatsumi et al.
patent: 4954729 (1990-09-01), Urai
IBM Technical Disclosure Bulletin, vol. 30, No. 7, Dec. 1987, CMOS Output Inverter Circuit with Low-Power Test Output Inverter, pp. 54-55.
G. Canepa et al, "A 90ns 4MB CMOS EPROM", 1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (Feb. 18, 1988): pp. 120, 121.

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