Buffer circuit operable with reduced power consumption

Details Buffer circuit operable with reduced power consumption Buffer circuit operable with reduced power consumption

1987-09-09

1990-01-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307482, 307578, 307355, 365203, 365205, H03K 1704, H03K 3356, H03K 1901, G11C 700

Patent

active

048945595

ABSTRACT:
A buffer circuit which can operate with reduced power consumption and at a high speed is disclosed. The buffer circuit is of the type having a flip-flop circuit with a pair of output terminals and a pair of boot-strap circuits each provided for each of the output terminals and having a capacitor and a precharge circuit for precharging the capacitor, and is featured in that a pair of control circuits are provided to the pair of boot-strap circuits. Each of the control circuits allows the capacitor to be charged when the associated output terminal is about to produce a high level signal and inhibits the capacitor from being charged when the associated output terminal is about to produce a low level signal.

REFERENCES:
patent: 4239993 (1980-12-01), McAlexander, III et al.
patent: 4397000 (1983-08-01), Nagami
patent: 4694205 (1987-09-01), Shu et al.
patent: 4701644 (1987-10-01), Campione
patent: 4719600 (1988-01-01), Huffman et al.
patent: 4733373 (1988-03-01), Murotani
patent: 4739499 (1988-04-01), Simpson

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