Buffer circuit on a module

Details Buffer circuit on a module Buffer circuit on a module

1998-06-24

1999-07-27

An, Meng-Ai T.

Sewing

Special machines

Leather sewing

712 29, 712 33, 712 39, 710 1, 710 5, G06F 900

Patent

active

059272180

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

1. The present invention relates to a buffer circuit arranged on a module for intermediate data storage.
2. Background Information
Decentralized systems are being increasingly used in automation technology. In such systems, input signals of a controlled industrial process are entered by decentralized peripheral modules and transmitted to a higher-level arithmetic unit located at a distance from the modules. The arithmetic unit can be, for example, the central processor of a stored-program controller. The arithmetic unit then processes the input signals and, from the input signals and possibly from additional internal values of the arithmetic unit, generates output signals that are subsequently forwarded via the field bus to the decentralized peripheral modules. These in turn output the output signals to the industrial process being controlled.
The input signals are input from the industrial process and the output signals are output to the industrial process by intelligent units in the peripheral modules, for example, microprocessors. The intelligent units are basically only responsible for sole function of inputting and outputting the signals.
The cycle time needed by the intelligent units for entering the input signals and outputting the output signals is normally very different from the time between two access periods of the higher-level arithmetic unit to the input signals or the output signals. Therefore, the input and output signals cannot be forwarded immediately from the intelligent unit of the peripheral module to the higher-level arithmetic unit and vice-versa, but must be temporarily stored in the decentralized peripheral module.


SUMMARY OF THE INVENTION

An object of the present invention is to provide a circuit arrangement which allows a higher-level arithmetic unit and an intelligent unit of the decentralized peripheral module to input data into and output from an intermediary storage device independently of one another and with no possibility of mutual blocking despite the intermediate storage.
The buffer circuit is normally arranged in an integrated circuit, e.g., a communication ASIC. The communication ASIC is normally also responsible for other communication functions, for which it must have additional storage space. Since ASIC storage space is still an expensive and scarce resource, the storage area available can be maximized by having variable-length buffer circuit storage areas.


BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a distributed automation system. FIG. 2 shows a buffer circuit according to the present invention.


DETAILED DESCRIPTION OF THE INVENTION

According to FIG. 1, central processor 1 of a stored-program controller is connected to decentralized peripheral module 3 via field bus 2. For purposes of clarity, only one peripheral module 3 is illustrated in FIG. 1.
Peripheral module 3 has an application-specific integrated circuit (ASIC) 4, which is connected to field bus 2 and, through lines 5 internal to the module, to a microprocessor 6. Microprocessor 6 represents an intelligent unit arranged on module 3.
Microprocessor 6 is connected, via input lines 7, to processor elements (not illustrated) of an industrial process 8, e.g., a burner control. Microprocessor 6 is also connected, via output lines 9, to process actuators (also not illustrated) of industrial process 8.
The communication ASIC 4, illustrated in detail in FIG. 2, contains the buffer circuit for intermediary storage of input and output signals in accordance with the present invention. According to FIG. 2, ASIC 4 has three input signal storage areas 10, 10', and 10", as well as three output signal storage areas 11, 11", and 11". Storage areas 10, 10', 10", 11, 11', and 11" are connected, via buses 12, to a selection circuit 13, which is in turn connected to a bus interface 17 and a module interface 18 via buses 14 and control lines 15, 16.
Input signals entered by microprocessor 6 from industrial process 8 are supplied, via module interface 18 and bus 14-1, to selection circuit 13, whic

REFERENCES:
patent: 4415985 (1983-11-01), McDaniel et al.
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 5740466 (1998-04-01), Geldman et al.

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