Buffer circuit of a semiconductor memory device

Details Buffer circuit of a semiconductor memory device Buffer circuit of a semiconductor memory device

1994-09-14

1995-11-21

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, G11C 11413

Patent

active

054694027

ABSTRACT:
An internal address signal is outputted quickly by connecting nMOS transistors in series to inverters forming a latching circuit of a row address buffer circuit, applying an external row address signal to the gate of a nMOS transistor, applying a delayed activation signal .phi.2 to the gate of the nMOS transistors, grounding the gate of the nMOS transistor, triggering nMOS transistors into complete conduction by the delayed activation signal .phi.2 to reduce the ON resistance. A column address buffer circuit receives a ZCAS circuit by an NOR gate, and an external column address signal by an NAND gate during standby, to prevent a flow of a through current.

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