Buffer circuit, memory device, and integrated circuit for receiv

Details Buffer circuit, memory device, and integrated circuit for receiv Buffer circuit, memory device, and integrated circuit for receiv

1998-05-13

2000-03-28

Hoang, Huan

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365207, 365205, 327 52, G11C 800

Patent

active

060440368

ABSTRACT:
A buffer circuit (60) that includes a current source (74) having an output, the current source to provide a substantially constant current, a first differential amplifier (62), and a second differential amplifier (66). The current from current source 74 is shared by the first (62) and second (64) differential amplifiers.

REFERENCES:
patent: 5032797 (1991-07-01), Mijuskovic
patent: 5729160 (1998-03-01), Allan
patent: 5881014 (1999-03-01), Ooishi
Richard J. Reay et al., "An Unconditionally Stable Two-Stage CMOS Amplifier", IEEE Journal of Solid-State Circuits, vol. 30, No. 5, May 1995, pp. 391-394.
Harold Pilo et al., "FA 9.3: A 300MHHz, 3.3V 1Mb SRAM Fabricated in a 0.5u m CMOS Process", IEEE/1996 Buena VistalSSCC Slide Supplement, 5 pgs.

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