Buffer circuit including a current leak circuit for maintaining

Details Buffer circuit including a current leak circuit for maintaining Buffer circuit including a current leak circuit for maintaining

1981-11-18

1984-05-08

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 307601, H03K 5135, H03K 19017, H03K 19096

Patent

active

044477457

ABSTRACT:
A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

REFERENCES:
patent: 4061933 (1977-12-01), Schroeder et al.
patent: 4239990 (1980-12-01), Hong et al.
patent: 4354123 (1982-10-01), Eaton, Jr.

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