Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1980-11-07
1982-08-31
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307578, 307594, 365227, H03K 17284, H03K 1716, H03K 17687
Patent
active
043474489
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to semiconductor memory circuits and more particularly to such a circuit which has a chip enable function to reduce the power consumption of the memory circuit.
BACKGROUND OF THE INVENTION
In many applications for semiconductor memory circuits there is only a limited supply of power available, generally a battery. In other applications the supply of power is not a limiting factor but the heat generated by an integrated circuit must be reduced to a minimum. It is in the practice to "power down" memory circuits when they are not in use to reduce the overall power consumption of a memory system.
In NMOS memory circuits, transistors with very low threshold voltages, low V.sub.t devices, have been used to power switch the positive power supply to the circuit. This reduces the power consumption by a substantial percentage but there is still considerable power consumed by the current leakage through the low V.sub.t devices.
Therefore, there exists a need for a buffer circuit which receives a signal to enable and disable a memory circuit and operates to drive the power transfer transistors in such a manner that the leakage current through these transistors is reduced to essentially zero.
SUMMARY OF THE INVENTION
An illustrative embodiment of the present invention utilizes a method and apparatus for controlling a plurality of power transfer transistors which supply power to operate semiconductor integrated circuits which can be "powered down" when not immediately needed. Circuitry is provided for charging a node which is connected to control the state of the power transfer transistors, the charging of the node carried out in response to a first enable signal. A second enable signal discharges the node down to a predetermined voltage. Further circuitry couples a negatively going clock signal to the node to drive the node to a voltage below the predetermined voltage whereby the power transfer transistors are rendered nonconductive. PG,5
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken into conjunction with the accompanying Drawings in which:
FIG. 1 is a schematic illustration of a chip enable buffer circuit for use in accordance with the present invention, and
FIG. 2 is an illustration of wave forms at selected nodes for the circuit shown in FIG. 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1 there is illustrated a chip enable circuit 10. The circuit 10 supplies power to various portions of a semiconductor memory circuit (not shown). The power for the various elements in the memory circuit is transferred through a plurality of transistors such as 12 and 14. The transistors 12 and 14 are fabricated to be natural field effect transistors as opposed to being either enhancement or depletion mode transistors. Therefore transistors 12 and 14 have essentially a zero threshold voltage and are turned off when the gate terminal is at essentially zero volts relative to the source terminal. Thus the parts of the semiconductor memory which are powered through the natural transistors 12 and 14 are deactivated whenever the gate terminals of the transistors are driven to zero voltage or below. When the semiconductor memory is being operated in the active mode the gate terminals of transistors 12 and 14 will be driven to essentially the supply voltage V.sub.cc, but when it is desired to deactivate elements of the semiconductor memory the gate terminals of transistors 12 and 14 will be driven slightly negative to insure that the transistors are fully turned off and that no power is being supplied to the elements in the semiconductor memory. This reduces the total power consumption of the integrated circuit incorporating circuit 10.
The gate terminals of transistors 12 and 14 are connected to a node which is charged to selected voltages to turn transistors 12 and 14 on and off.
A chip enable (CE) signal is supplied through a
REFERENCES:
patent: 3778784 (1973-12-01), Karp et al.
patent: 3906464 (1975-09-01), Lattin
patent: 4019068 (1977-04-01), Bormann
patent: 4259594 (1981-03-01), Fox et al.
Gray et al., "Power Supply Stabilization Circuit", IBM Tech. Discl. Bull., vol. 21, No. 4, pp. 1384-1385, 9/78.
Anagnos Larry N.
Mostek Corporation
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