Buffer circuit for minimizing noise in an integrated circuit

Details Buffer circuit for minimizing noise in an integrated circuit Buffer circuit for minimizing noise in an integrated circuit

1987-01-05

1988-06-28

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, 307555, 307568, 307577, 307264, 307270, H03K 1716, H03K 17693

Patent

active

047541709

ABSTRACT:
In the buffer circuit for an integrated circuit according to this invention a load MOS transistor and a drive MOS transistor are connected in series between a power source potential node and a ground potential node of the integrated circuit. A constant current circuit means connected in series with a circuit including the load MOS transistor and the drive MOS transistor.

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patent: 4587445 (1986-05-01), Kanuma
patent: 4609834 (1986-09-01), Gal
patent: 4628218 (1986-12-01), Nakaizumi
patent: 4656370 (1987-04-01), Kanuma
Moshen et al., "The Design and Performance of CMOS 256K Bit DRAM Devices," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 610-618, Oct. 1984.

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