Buffer circuit for minimizing noise in an integrated circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307448, 307451, 307555, 307568, 307577, 307264, 307270, H03K 1716, H03K 17693

Patent

active

047541709

ABSTRACT:
In the buffer circuit for an integrated circuit according to this invention a load MOS transistor and a drive MOS transistor are connected in series between a power source potential node and a ground potential node of the integrated circuit. A constant current circuit means connected in series with a circuit including the load MOS transistor and the drive MOS transistor.

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Moshen et al., "The Design and Performance of CMOS 256K Bit DRAM Devices," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 610-618, Oct. 1984.

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