Buffer circuit for logic level conversion

Details Buffer circuit for logic level conversion Buffer circuit for logic level conversion

1991-03-14

1992-03-24

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307455, H03K 19017, H03K 1920

Patent

active

050991515

ABSTRACT:
A semiconductor interface circuit comprises a threshold circuit supplied with an input logic signal and an internal reference signal for discriminating the logic level thereof, and a reference circuit supplied with an external reference voltage for producing the internal reference signal. The threshold circuit comprises a first load, a first enhancement mode FET and a second load connected in series between a first power terminal and a second power terminal, wherein the internal reference signal is supplied to the gate of the first enhancement mode FET. Further, a first FET having a gate to which the input logic signal is supplied, is provided between the first and second power supply terminals. The first FET produces the output at the drain thereof. The reference circuit comprises a third load, a second enhancement mode FET and a fourth load connected in series between the first and second power terminals, wherein the drain and the gate are connected. Further, a second FET is provided across the first and second power terminals. The second FET is supplied with the reference voltage at a gate thereof, and the internal reference voltage is obtained at the drain of the second enhancement mode FET.

REFERENCES:
patent: 4845381 (1989-07-01), Cuevas
patent: 4845388 (1989-07-01), Amatangelo
patent: 5015888 (1991-05-01), Ovens
patent: 5019729 (1991-05-01), Kimura et al.
patent: 5021691 (1991-06-01), Saito

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