Buffer circuit for logic level conversion

Details Buffer circuit for logic level conversion Buffer circuit for logic level conversion

1990-11-09

1991-09-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307450, 307542, 307572, 307574, H03K 190175

Patent

active

050516264

ABSTRACT:
An input buffer circuit for converting a logic level of an input logic signal comprises an inversion circuit and a level shift circuit in which the inversion circuit comprises an input terminal to which the input signal is applied, a first voltage source for supplying a first predetermined voltage, a second voltage source for supplying a second predetermined voltage having a level lower than that of the first predetermined voltage, a first resistor circuit having a first end connected to the first voltage source, a first enhancement type field effect transistor having a drain connected to a second end of the first resistor circuit, a source connected to the second voltage source and a gate connected to the input terminal, a second resistor circuit having a first end connected to the first voltage source, and a second enhancement type field effect transistor having a drain connected to a second end of the second resistor circuit, a source connected to the drain of the first enhancement type field effect transistor and a gate connected to the gate of the first enhancement type field effect transistor.

REFERENCES:
patent: 4767951 (1988-08-01), Cornish et al.
patent: 4791322 (1988-12-01), Graham et al.
Laude, D. P., "An ECL Compatible GaAs 504 4-Input Nor Gate Array", Proceedings of the IEEE 1986 Custom Integrated Circuits Conference, May 12-15, 1986, pp. 508-512.

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