Buffer circuit for driving a C-MOS inverter

Details Buffer circuit for driving a C-MOS inverter Buffer circuit for driving a C-MOS inverter

1982-08-13

1985-05-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307576, 307585, 307594, 307475, H03K 17284, H03K 1726, H03K 17687, H03K 1716

Patent

active

045188734

ABSTRACT:
A buffer circuit for driving a C-MOS inverter, including a first inverter and a second inverter for driving a p-MOS transistor, respectively, and an n-MOS transistor in the C-MOS inverter. Each of the inverters includes at least three transistors connected in series. At least one of the three transistors in each inverter is driven by a delay circuit so that during a transition period of the C-MOS inverter, simultaneous conduction of current through the C-MOS inverter is prevented.

REFERENCES:
patent: 3551693 (1970-12-01), Burns et al.
patent: 3631528 (1971-12-01), Green
patent: 3851189 (1974-11-01), Moyer
patent: 4164842 (1979-08-01), Ebihara
patent: 4317180 (1982-02-01), Lies
patent: 4329600 (1982-05-01), Stewart
patent: 4366398 (1982-12-01), Asami
Electronics and Communications in Japan, "Performance of Logic LSIs Using Short Channel MOSFETs", by Minato et al., vol. 60-C, No. 9, Sep. 1977, pp. 102-109.

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