Buffer circuit design using back track searching of site trees

Boots – shoes – and leggings

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364488, G06F 1560

Patent

active

054023564

ABSTRACT:
A buffer circuit for fanning out a source signal to a plurality of terminals of specified polarities in accordance with specified time constraints is designed by an automated method in which a circuit template is specified in terms of a tree structure. The terminals are ordered in increasing order of required arrival times of the source signal at each of the terminals. A first terminal in a resulting order is assigned to a highest-level potential terminal site of a same polarity as said first terminal, and buffers on a signal path between said first terminal and the source signal are sized so as to satisfy, if possible, a required arrival time of the source signal at said first terminal. So long as required times of arrival are met, additional terminals are placed in like manner. The method proceeds as far as possible using a straight forward assignment procedure of terminals to potential terminal sites, then backtracks, undoing so much of the previous assignments as necessary and making incremental adjustments to allow the method to proceed further if possible. The method is completed when either all terminals have been successfully assigned or all of the previous assignments have been undone.

REFERENCES:
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patent: 4890016 (1989-12-01), Tanaka et al.
patent: 5109168 (1992-04-01), Rusu
patent: 5187784 (1993-02-01), Rowson
C. L. Berman, et al. "The Fanout Problem: From Theory to Practice". Advanced Research In VLSI, Proceedings of the Decennial CalTech Conf. on VLSI Mar. 1989, ed. Charles L. Seitz, 69-99.
K. J. Singh, et al. "A Heuristic Algorithm for the Fanout Problem". 27th ACM/IEEE Design Automation Conf., 1990, 357-360.
H. J. Touati, et al., "Performance-Oriented Technology Mapping" Advanced Research In VLSI, Proceeedings of the Sixth MIT Conf., 1990, ed. W. J. Dally, 79-97.

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