Static information storage and retrieval – Powering
Reexamination Certificate
2000-06-12
2001-11-13
Nguyen, Matthew (Department: 2838)
Static information storage and retrieval
Powering
C323S281000
Reexamination Certificate
active
06317378
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a buffer circuit for buffering a supply voltage of an integrated circuit.
Such buffer circuits usually contain capacitors for buffering the voltage. If the capacitor has a defect, that is to say an undesirable leakage current flows through it, the buffer circuit can no longer fulfill its function. That is because the defective capacitor then causes a collapse of the voltage to be buffered. In the text below, a defect in a capacitor is understood to mean a state in which a current flow occurs between the two electrodes of the capacitor. Such a defect may be caused, for example, by production faults or by overvoltages occurring during subsequent operation with the consequence of damage to the dielectric of the capacitor.
Summary of the Invention
It is accordingly an object of the invention to provide a buffer circuit for a supply voltage of an integrated circuit, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which has a large tolerance with respect to defects of buffer capacitors contained in the buffer circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a buffer circuit for buffering a supply voltage of an integrated circuit, comprising two potential nodes between which a supply voltage drops; a series circuit disposed between the two potential nodes, the series circuit having at least two buffer capacitors and a third potential node disposed between the buffer capacitors; and an additional circuit connected to the third potential node for influencing a potential at the third potential node to not exceed an upper and/or a lower limit value upon occurrence of a leakage current through one of the capacitors.
The series circuit which is formed by two capacitors for buffering the supply voltage makes it possible to buffer a higher voltage than would be possible with just one of the two capacitors. Without the additional circuit according to the invention, in the event of a defect in one of the two buffer capacitors, due to the voltage dip associated therewith, a very high voltage would be dropped across the still intact second capacitor. In many cases that would result in even the second capacitor being destroyed, with the result that a short-circuit current would then flow through both capacitors. The supply voltage to be buffered would collapse in that case.
The additional circuit according to the invention ensures that the potential between the two buffer capacitors, in the event of a defect in one of the capacitors, is not solely dependent on the short-circuit resistance thereof, but also additionally on the additional circuit. The effect that is achieved due to the limitation of the changes in the potential at the third potential node which occur in the event of defects is that the level of the voltage dropped across the still intact capacitor likewise remains limited. Field strengths which could cause the destruction of the still intact capacitor are avoided in this way. Consequently, in an advantageous manner, the buffer circuit remains at least partially effective even if one of the two buffer capacitors is defective, and without the supply voltage to be buffered collapsing due to a short circuit through both capacitors of the buffer circuit.
In accordance with a first embodiment of the invention, the additional circuit has a resistance element, through which the third potential node is connected to an essentially constant potential. The potential at the third potential node then corresponds, in the case of intact buffer capacitors, essentially to the constant potential. If one of the buffer capacitors is defective, the potential at the third potential node is determined in a manner dependent on the voltage divider ratio which is formed by the resistance element and the short-circuit resistance of the defective buffer capacitor. The value of the resistance element should be dimensioned correspondingly, so that the potential at the third potential node varies only within the desired limits when a defect occurs. In this case, the resistance element is dimensioned with reference to short-circuit resistances which are typical of the capacitors used when a defect is present.
If the two buffer capacitors are dimensioned identically, it is advantageous to place the value of the constant potential exactly in the middle between the potentials at the first and second potential nodes. In that case, given an intact buffer circuit, half of the supply voltage to be buffered is dropped across each of the buffer capacitors and no current flows through the resistance element.
The high-value resistance element may be realized, for example, by a non-reactive resistor, by a diode or by a transistor connected as a resistor.
In accordance with a further feature of the invention, the resistance of the high-value resistance element can be adjusted through the use of a voltage regulator which regulates the potential of the third potential node in this way, in such a way that it does not exceed the upper and/or lower limit values. This affords the advantage over a solution with a non-adjustable resistance element of permitting the potential at the third potential node to be kept stable for the extremely varied short-circuit resistances of the defective capacitor.
In accordance with an added feature of the invention, the additional circuit has a voltage divider which is disposed between fourth and fifth potential nodes and across which an essentially constant voltage is dropped, and the voltage divider has two resistance elements between which a sixth potential node connected to the third potential node isdisposed.
In accordance with an additional feature of the invention, the fourth potential node is connected to the first potential node and the fifth potential node is connected to the second potential node. In that case, the constant voltage dropped across the voltage divider is identical to the supply voltage to be buffered, and a further constant voltage is not required.
In accordance with a concomitant feature of the invention, it is particularly favorable if at least one, but preferably both, of the resistance elements of the voltage divider have variable resistances. Corresponding control inputs of the resistance elements are connected to a voltage regulator which regulates the potential at the third potential node through the resistance elements.
The embodiments of the invention that have been outlined, in which the additional circuit has a voltage regulator, have the major advantage of allowing the potential at the third potential node to be predetermined with a high degree of accuracy in the event of a defect in one of the buffer capacitors. The adaptation of the voltage divider ratio for the third node so as to be dependent on the value of the short-circuit resistance of the defective capacitor prevents damage to the non-defective capacitor for extremely varied values of short-circuit resistance of the defective capacitor.
The invention is advantageous particularly when the buffer circuit has a plurality of series circuits each including two buffer capacitors of the type described, in which the potential node located between the buffer capacitors is either connected to a separate additional circuit or is in each case connected to the third potential node of the first series circuit. As a result, all of the series circuits are influenced by only one additional circuit. Even if the buffering capacity of one of the series circuits is restricted due to a defect in one of its buffer capacitors, the remaining series circuits can then ensure the buffering of the supply voltage virtually without any restriction.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a buffer circuit, it is nevertheless not intended to be limited to the details shown, since various modificatio
Feurle Robert
Savignac Dominique
Schneider Helmut
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Matthew
Stemer Werner H.
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