Buffer circuit

Details Buffer circuit Buffer circuit

1979-08-08

1982-09-07

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307562, 307568, 365103, 365189, G11C 706, G01R 19165, H03K 524, H03K 508

Patent

active

043486010

ABSTRACT:
A buffer circuit operable with high speed is disclosed. The circuit comprises an input node, an amplifying means having an input coupled to the input node, a first power source, a second power source, a first transistor coupled between the first potential source and the input node, a second transistor coupled between the input node and the second power source, and means responsive to the output of the amplifying means for respectively providing a first signal and a second signal complementary to the first signal to the gates of the first and second transistors so as to restrict a potential amplitude at the input mode.

REFERENCES:
patent: 3560765 (1971-02-01), Kubinec
patent: 3648071 (1972-03-01), Mrazek
patent: 3728556 (1973-04-01), Arnell
patent: 3932848 (1976-01-01), Porat
patent: 4039860 (1977-08-01), Lambrechtse et al.
patent: 4124808 (1978-11-01), Shieu et al.
patent: 4136292 (1979-01-01), Suzuki et al.
McKenny, Electronics, pp. 80-85, Feb. 12, 1971.

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