Buffer circuit

Details Buffer circuit Buffer circuit

2005-07-18

2009-08-18

Lam, Tuan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S539000

Reexamination Certificate

active

07576595

ABSTRACT:
The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power consumption. A current input to npn transistor Q1via node N1is detected by current detection circuit1.At bias control circuit2,base voltage of npn transistor Q2is regulated in such a manner that the current of npn transistor Q2decreases in accordance with an increase in said detected current, and the current of npn transistor Q2increases in accordance with a decrease in the detected current. As a result, because transient current which can flow to the load can be increased, even when load capacitor CL has a large capacitance or when the frequency is high, the output voltage can quickly follow a change in the input voltage, so that distortion of the output voltage waveform can be restrained.

REFERENCES:
patent: 5874858 (1999-02-01), Furuya
patent: 6064274 (2000-05-01), Nayebi et al.
patent: 6271716 (2001-08-01), Nayebi et al.
patent: 7098720 (2006-08-01), Dow
patent: 7221217 (2007-05-01), Choi et al.
patent: 2004/0095198 (2004-05-01), Yeh

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