Bucket-brigade delay line having reduced parasitic capacitances

Details Bucket-brigade delay line having reduced parasitic capacitances Bucket-brigade delay line having reduced parasitic capacitances

1976-07-30

1977-08-30

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307221D, H01L 2978, G11C 1928

Patent

active

040458105

ABSTRACT:
An MOS bucket brigade delay line having reduced parasitic capacitances include a first set of diffused drain source regions in a semiconductor substrate, a thin gate oxide layer overlying said diffused regions, a plurality of gate electrodes having first and second edges, the first edge of each electrode substantially overlapping one of said diffused regions, each of these elements formed in conventional manner. A second set of diffused drain-source regions extends the first set of regions by an amount limited by the second edge of the gate electrodes. The second set of drain source regions is formed by utilizing the gate electrodes as a diffusion mask.

REFERENCES:
patent: 3790825 (1974-02-01), Barrow et al.
patent: 3933529 (1976-01-01), Goser
patent: 3936857 (1976-02-01), Ota
Agusta et al., "Structure & Fabrication of Self-Aligned Bucket Brigade," IBM Technical Disclosure Bulletin, vol. 15, (6/72), pp. 12-13.
Sangster, "The Bucket Brigade and Other Charge Transfer Devices," Proc. 5th Conf. on Solid State Devices, Tokyo (8/73), Publ. in Supplement to J. Japan Soc. Applied Physics, vol. 43, (4/74), pp. 275-281.

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