Buck-boost circuit with normally off JFET

Electricity: power supply or regulation systems – In shunt with source or load – Using a three or more terminal semiconductive device

Reexamination Certificate

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Reexamination Certificate

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07098634

ABSTRACT:
An enhancement mode JFET as a switching device in a buck-boost converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocking state. The ratio of converter output voltage to converter input voltage is determined by the ratio of JFET current blocking time to the sum of JFET conduction time and JFET blocking time. This pulse width modulation scheme is thus used to adjust the dc output voltage level.

REFERENCES:
patent: 4347474 (1982-08-01), Brooks et al.
patent: 4808853 (1989-02-01), Taylor
patent: 4853561 (1989-08-01), Gravok
patent: 5055723 (1991-10-01), Bowers et al.
patent: 5180964 (1993-01-01), Ewing
patent: 5359280 (1994-10-01), Canter et al.
patent: 6251716 (2001-06-01), Yu
patent: 6356059 (2002-03-01), Yu
patent: 6580252 (2003-06-01), Yu
patent: 6696706 (2004-02-01), Pegler
H. Ogiwara, M. Hayakawa, T. Nishimura and M. Nakaoka; “High-Frequency Induction Heating Inverter with Multi-Resonant Mode Using Newly Developed Normally-Off Type Static Induction Transistors”; Department of Electrical Engineering, Ashikaga Institute of Technology, Japan; Department of Electrical Engineering, Oita University, Japan; Department of Electrical of Engineering, Kobe University, Japan; pp. 1017-1023; This paper appears in: Power Electronics Specialists Conference, 1993, PESC 93 record, 24thAnnual IEEE, pp. 1017-1023, Jun. 20-24, 1993.
J. Baliga; “High-Voltage Junction-Gate Field Effect Transistor with Recessed Gates”; IEEE Transactions on Electron Devices; vol. ED-29; No. 10; Oct. 1982, no page #'s.
J. M. C. Stork et al.; “Small Geometry Depleted Base Bipolar Transistors (BSIT)-VLSI Devices?”; IEEE Transactions on Electron Devices; vol. ED-28; No. 11; Nov. 1981, no page #'s.
Nishizawa et al.; “Analysis of Static Characteristics of a Bipolar-Mode SIT (BSIT)”; IEEE Transactions on Electron Devices; vol ED-29; No. 11; Aug. 1982, 1233-1244.
Caruso et al.; “Performance Analysis of a Bipolar Mode FET (BMFET) with Normally Off Characteristics”; IEEE Transactions on Powe Electronics; vol. 3, No. 2; Apr. 1988, 3-4, 157-163.
Nishizawa et al.; “Field Effect Transistor Versus Analog Transistor (Static Induction Transistor)”; IEEE Transactions on Electron Devices; vol. ED-24; No. 4; Apr. 1975, no page #'s.

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