Coded data generation or conversion – Digital code to digital code converters – To or from constant distance codes
Reexamination Certificate
2000-05-17
2002-05-28
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from constant distance codes
C341S050000
Reexamination Certificate
active
06396424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to parallel analog-to-digital converters (ADCs) and more particularly to techniques for reducing output errors on a flash ADC.
2. Description of the Related Art
The objective of analog-to-digital (“ADC”) converters is to receive an analog signal and produce an error free digitized version of that analog signal. A well known ADC circuit is a parallel or “flash” ADC, which receives an analog signal to be digitized and compares its voltage to a set of reference voltages. As illustrated in
FIG. 1
, for “n” bits of resolution in the ADC's digital output, a known voltage is applied to a ladder of 2
n
series resistors
110
to provide reference voltages at the nodes between the resistors
110
. Comparators
120
, typically implemented with high gain amplifiers, receive respective reference voltages at one input and the analog input signal at another input to produce either a low output (binary 0) if the comparator's reference voltage is greater than the analog input, or a high or “active” output (binary 1) if the analog input is higher than the comparator's reference voltage. Ideally, the resulting digital comparator
120
outputs, referred to as “thermometer code,” are a series of binary 0s for comparators which receive reference voltages greater than the analog input signal, and a series of binary is for comparators which receive a reference voltage less than the analog input signal. The transition from binary 0s to 1s indicates the amplitude of the analog input signal.
In a typical flash-type Analog-to-Digital Converter (ADC) shown in
FIG. 1
, the task of the digital back-end is to process the thermometer code output of the 2
n
−1 comparators
120
and generate an equivalent n-bit digital binary output. There are numerous ways of achieving this goal. One commonly used scheme is to configure a 1-of-(2
n
−1) decoder
130
followed by a Read-Only-Memory (ROM)
140
look-up table. The decoder
130
detects the 0-to-1 transition in the thermometer code output of the comparators
120
and activates the corresponding output line which enables a ROM address to place its contents on the output data-bus.
When high slew-rate input signals are sampled, timing skew between the clock and signal paths and differences in comparator
120
response-times can cause the effective strobe point of the comparators to be different. This can lead to an irregular thermometer code pattern where a 0 can be found below a 1 or a 1 above a 0. These unwanted irregularities are known as “bubbles” and if they are not adequately suppressed they can cause severe ROM output errors, known as “sparkle” code errors, as more than one address can become enabled at the same time. These large output errors can have significant impact on the Signal-to-Noise Ratio (SNR) performance of the ADC.
Several methods of preventing bubbles from causing sparkle code errors have been reported. The suppression scheme may be implemented in the 1-of-(2
n
−1) decoder and/or in the ROM. Some of the well known schemes include “Democratic Decoding” (C. W. Mangelsdorf, “A 400 MHz Input Flash Converter with Error Correction”, IEEE J. Solid-State Circuits, vol. 25, pp. 184-191, February 1990); “Quasi-Gray” Code (Y. Akazawa et al., “A 400MSPS 8-bit Flash A/D Conversion LSI”, in ISSCC Dig. Tech. Papers, pp. 98-99, February 1987); “Half-Gray” Code (U.S. Pat. No. 5,633,636. Title: Half-Gray Digital Encoding Method and Circuitry”. Date: May 27, 1997); “Bit-Swap” techniques (V. E. Garuts et al., “A Dual 4-bit 2Gs/s Full Nyquist Analog-to-Digital Converter using a 70 ps Silicon Bipolar Technology with Borosenic-Poly Process and Coupling-Base Implant”, IEEE J. Solid-State Circuits, vol. 24, pp. 216-222, April 1989); and several multi-level ROM topologies. Most of these schemes, however, are quite complex and more suitable to lower sampling rates or, alternatively, require a high-speed bipolar technology which will dissipate large amounts of power.
SUMMARY OF THE INVENTION
A bubble suppression apparatus is disclosed comprising: a first set of AND gates, wherein each AND gate within the first set has an input configured to receive a binary thermometer code value and one or more adjacent binary thermometer code values; and a second set of AND gates, wherein each AND gate within the second set has an input coupled to two or more outputs of the first set of AND gates.
REFERENCES:
patent: 4733220 (1988-03-01), Knierim
patent: 5257270 (1993-10-01), Hilden et al.
patent: 5329279 (1994-07-01), Barbu et al.
patent: 5633636 (1997-05-01), Reyhani
“An 8-b ADC with Over-Nyquist Input at 300-Ms/s Conversion Rate”, Nejime, et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 9, Sep. 1991, pp. 1302-1308.
“A 400-MHz Input Flash Converter With Error Correction”, Christopher W. Mangelsdorf, IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 184-191.
“A Dual 4-Bit 2-Gs/s Full Nyquist Analog-to-Digital Converter Using a 70-ps Silicon Bipolar Technology with Borosenic-Poly Process and Coupling-Base Implant”, Garuts, et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 216-222.
“A Monolithic 8-Bit A/D Converter with 120 MHz Conversion Rate”, Inoue, et al., IEEE Journal of Solid-State Circuits, vol. 19, No. 6, 12-84, pp. 837-841.
“An 8b 350 MHz Flash ADC”, 1987 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Yoshii, et al., Feb. 1987, pp. 1-2 & 96-97.
“A 400MSPS 8b Flash AD Conversion LSI”, 1987 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Akazawa, et al., Feb., 1987, pp. 98-99 & 1-2.
“A 10b 20Ms/s 3V-Supply CMOS A/D Converter For Integration into System VLSIs”, 1994 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Miki, et al., pp. 48-49 & 1-2.
Horan John
Reyhani Hooman
Ryan John G.
Blakely , Sokoloff, Taylor & Zafman LLP
Jeanpierre Peguy
Lauture Joseph
Parthus Ireland Limited
LandOfFree
Bubble suppression method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bubble suppression method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bubble suppression method and apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2846408