Bubble memory defect tolerant logic control circuit

Details Bubble memory defect tolerant logic control circuit Bubble memory defect tolerant logic control circuit

1977-11-03

1980-05-06

Moffitt, James W.

Static information storage and retrieval

Magnetic bubbles

Plural interacting paths

365 12, G11C 1908

Patent

active

042020433

ABSTRACT:
A bubble memory system comprising data chips each having a plurality of storage loops and wherein each is provided with additional storage loops to compensate for defective loops in the chip, and a control chip having control loops, one loop for each data chip and with bit positions corresponding in number to the number of storage loops in the data chip and connected to the data chip to prevent defective loops on the data chips from being utilized. Thus, data chips which would otherwise have been discarded as defective can now be used.

REFERENCES:
patent: 3792450 (1974-02-01), Bogar
patent: 4073012 (1978-02-01), Ohnigian et al.
IBM Technical Disclosure Bulletin--vol. 18, No. 9, Feb. 1976, pp. 3079-3081.

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