Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-08-23
2002-05-14
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S160000, C341S155000, C341S156000, C341S158000, C341S059000, C341S097000
Reexamination Certificate
active
06388602
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an encoding circuit, and more particularly to a bubble error and meta-stability error immune gray-code encoder for high-speed analog-to-digital (A/D) converters.
2. Description of the Related Art
High-speed analog-to-digital converters (ADCs) encounter two typical problems. A first problem is the meta-stability in comparators resulting in output errors, which is due to the relatively small difference in the input of the comparators and not enough time to amplify the small input difference to the large logic levels.
That is, metastability errors occur in A/D converters when undefined comparator outputs pass through an encoder to the converter output bits. In flash converters, 2
n
−1 comparators are presented with a voltage different V
REF(i)
−V
A
and latched every clock cycle. Under normal operating conditions, the comparator outputs generate a “thermometer code,” where comparators with reference voltages above V
A
have an output of “0” and the rest of the comparators have an output of “1”. Thermometer code detection logic turns on the appropriate word line in the encode ROM. However, if V
A
is near the reference voltage for a comparator, the comparator output may be undefined at the end of the valuation time. Since V
A
typically has a continuous amplitude, there is always a finite probability that the voltage difference cannot be amplified sufficiently in the time allotted for comparison. If the output is not sufficiently amplified, indeterminate digital signals are propagated to the encoder logic, thereby leading to errors.
Thus, metastability errors result in invalid or metastable logic states which may cause logical errors in the encoding circuit, thereby producing an output code not representative of the input voltage applied to the A/D converter.
Another problem is the so-called bubble error, which is due to the non-monotonic output code generated from the comparator array.
Referring to
FIG. 1
, a conventional binary code encoder
10
is shown which can reduce the bubble errors. In operation, the comparator outputs t
i
form a thermometer code in the normal operation, which is . . . 000111 . . . and a logic circuit (e.g., including NAND gates
11
and transistors
12
) detects 0-1 transition out of the bit pattern, and converts it into a so-called 1-of-n code, which appears as . . . 0001000 . . . However, if a bubble error is introduced in the thermometer code, there can be two (or more) 1-0 transition points in the code, for example, . . . 00010111 . . . The logic circuit in
FIG. 1
detects a 011 pattern instead of a 01 pattern so that it can eliminate the effect due to the bubble error. The converted 1-of-n code is converted to a binary code in the binary encoding ROM composed of transistors
12
as shown in FIG.
1
. However, this conventional encoder cannot reduce the meta-stability related errors (e.g., see K. Ono., et al., “Error Suppressing Encode Logic of FCDL in a 6-b Flash A/D Converter,” IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1460-1464, September 1997), because the metastable signal can propagate to the more significant bit (MSB), thereby resulting in a large output digital error (e.g., a so-called “meta-stability error”), as shown in FIG.
2
.
Meta-stability errors can be reduced by having more pipe-lined comparator stages to increase the regeneration time and gain (e.g., see B. Zojer, R. Petschacher, and W. A. Luschning, “A 6-bit/200-MHz full Nyquist A/D converter,” IEEE J. Solid-State Circuits, Vol. SC-20, No. 3, pp. 780-786, June 1985). However, this configuration will increase the latency, power consumption, and also the area of the ADC, as the number of pipelined stages is increased.
A gray code encoding scheme can be employed to reduce the meta-stability errors. There are some examples of gray code encoders (e.g., see Ono et al. mentioned above and U.S. Pat. No. 4,733,220 to Knierim et al.) that can reduce the meta-stability related errors.
Typically, ADCs incorporating such gray code encoders are for converting an analog voltage signal to an n-bit (e.g., four-bit) Gray code signal of equivalent magnitude. The ADC typically includes an analog-to-thermometer code converter, a thermometer-to-Gray encoder and a set of latches coupling the output of the code converter to the input of the encoder.
The Gray code is a well known non-weighted, adjacent binary code, wherein only one bit is changed to increment or decrement the value of a number represented by the code. The analog-to-thermometer code conversion circuit typically includes a set of comparators and a voltage divider network. An analog voltage signal to be sampled is applied to a non-inverting input of one of the comparators while a reference voltage VREF is applied to the voltage divider network, thereby producing progressively lower reference voltage quantum levels applied to inverting inputs of each comparator. Each comparator includes a different amplifier having an output which saturates to a high (e.g., logical “1”) comparator output state if the input voltage is sufficiently higher than its voltage reference level, or saturates to a low (e.g., “0”) comparator output state if the input voltage is sufficiently closer than its reference voltage.
Thus, the comparators produce outputs t
1
-t
N
, which collectively appears as N-bit thermometer code representing the magnitude of the input voltage as any of N+1 discrete number including 0. The outputs t
1
-t
N
are in turn latched into the input of the encoding circuit on receipt of a clock signal, and then the encoder converts the thermometer code to the more compact and useful Gray code. The conventional encoder includes AND gates providing an input to an OR gate (e.g., 4 OR gates producing a 4-bit Gray code).
However, such gray code encoding schemes are very susceptible to bubble errors.
For purposes of the present invention, a “bubble error” is defined as an error occurring as a result of hardware mismatches in which the threshold of a comparator is designed to be linear, but in reality there are errors such as clock errors resulting in the different sampling time among the comparators, offset voltage in the comparators resulting in the change of threshold voltage, etc. Thus, in normal operation, when a comparator with a higher threshold gives a “1” at an output, then another comparator having a lower threshold should also provide an output of “1”. However, with any type of error, the lower threshold comparator may provide at its output, a “0” instead of a “1”. Thus, errors (e.g., so-called bubble errors) in the gray code encoder may cause a faulty output and operation of the system.
Thus, the output codes with the bubble errors in the comparator array may cause digital output errors. Typical ADCs using binary code encoder can be implemented with a bubble correction circuit that observes a few of the comparator outputs at once to detect the location of the bubble and suppresses it as in Ono et al.
However, prior to the present invention, there have been few, if any, acceptable gray encoding schemes for solving both bubble errors and meta-stability errors.
For example, Portmann et al. (e.g., C. L. Portmann, T. H. Y. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,” IEEE J. Solid-State Circuits, Vol. 31, No. 8, pp. 1132-1140, August. 1996) uses a gray encoding scheme that can both reduce the bubble errors as well as the meta-stability error. However, due to the additional stage of a “completion detection circuit” required in the encoder, the operating speed is reduced and additional circuit “real estate” is required.
Thus, hitherto the invention, there have been no acceptable schemes for solving both bubble errors and meta-stability errors, without reducing an operating speed and efficiency of the system.
That is, as the conversion rate and the resolution of the ADC go higher, it has more problems of meta-stability in the comparator array because the time to amplify and regenerate the i
Mai Lam T.
McGinn & Gibb PLLC
Otterstedt, Esq. Paul J.
Tokar Michael
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