Brushless motor speed detector

Electricity: motive power systems – Limitation of motor load – current – torque or force

Patent

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Details

318138, 318254, 388800, A01R 3946

Patent

active

056442033

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

a) Field of the Invention
The present invention relates to a brushless motor speed detector requiring no frequency generator (hereinafter referred to as FG) pattern or FG magnetization.
b) Description of the Related Art
An FG is widely used as a speed detector for various motors. FIGS. 10 to 13 show examples of the FG. In FIG. 10, a stator core 2 radially having a proper number of salient poles is secured onto a motor substrate 1 and a driving coil 3 is wound on each salient pole of the stator core 2. Moreover, an FG pattern 4 is formed on the substrate 1 like a rectangular wave along a circle concentric with and outside of the stator core 2. Furthermore, a motor driving IC 5 is arranged on the substrate 1.
A rotor 6 shown in FIGS. 11 and 12 is arranged on the stator core 2 and the FG pattern 4 so as to cover them. The rotor 6 comprises a compressed-cup-shaped rotor case 7 and an annular driving magnet 8 secured to the inside annular wall of the case 7. The rotor 6 is rotatably supported by the substrate 1 through a proper bearing at a proper interval between the external surface of each salient pole of the stator core 2 and the internal surface of the driving magnet 8. In FIG. 11, the bottom of the driving magnet 8 is magnetized at certain intervals in the circumferential direction to form an FG magnetizing section 9. The FG magnetizing section 9 faces the FG pattern at a certain interval.
In FIGS. 10 and 13, an output terminal 4a of the FG pattern 4 is connected to an input terminal of an FG amplifier 5a in the motor driver IC 5. Power is generated by each power generating section when the rotor 6 rotates and the magnetic flux emitted from the FG magnetizing section 9 crosses each power generating section of the FG pattern 4 and a signal with a frequency proportional to a motor speed is provided as an output from the output terminal 4a of the FG pattern 4. The output signal is waveform-shaped and amplified by the FG amplifier to serve as a speed detection signal. The speed detection signal is supplied as an output to a motor speed control circuit.
Therefore, the FG has widely been used as a general motor speed detector. To constitute the FG, an FG pattern and FG magnetization are necessary, thereby motor structure is restricted and cost also increases. A motor speed detector requiring no FG pattern or FG magnetization has been proposed. Some motor speed detectors are disclosed in the official gazettes of Japanese Patent Laid-Open No. 97294/1990, Japanese Utility Model Laid-Open No. 54499/1992, Japanese Patent Laid-Open No. 277191/1991, and Japanese Patent Laid-Open No. 193084/1992 in which the midpoint voltage of a driving coil and the counterelectromotive voltage of each phase driving coil are compared by a comparator to detect the alternate change point of the counterelectromotive voltage and provide a signal as an output corresponding to the detected point as a speed detection signal.
FIG. 14 shows an example of basic structures of the speed detectors.
In the case of the brushless motor, three-phase sine-wave signals corresponding to the relative positional relation between a stator having driving coils L.sub.U, L.sub.V, and L.sub.W and a not-illustrated rotor having magnetic poles are provided as as outputs from a not-illustrated Hall element to a brushless motor driving circuit 10 and the rotor rotates when a driving current is provided as an output from the brushless motor driving circuit 10 to the driving coils L.sub.U, L.sub.V, and L.sub.W.
The brushless motor is provided with a speed detector comprising a comparator group 16 and a logic circuit 17. That is, comparators 16a, 16b, and 16c for comparing the output voltage of each phase with the coil midpoint voltage are connected to the output terminals of the driving coils L.sub.U, L.sub.V, and L.sub.W respectively; AND gates 17a, 17b, and 17c using two of outputs from the comparators 16a, 16b, and 16c as their inputs are connected to the output terminals of the comparators 16a, 16b, and 16c respectively; and an OR gat

REFERENCES:
patent: 5426354 (1995-06-01), Bausch
patent: 5433541 (1995-07-01), Hieda et al.
patent: 5467173 (1995-11-01), Sakata et al.
patent: 5477121 (1995-12-01), Sirjola

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