Brokaw transconductance operational transconductance...

Details Brokaw transconductance operational transconductance... Brokaw transconductance operational transconductance...

1999-12-23

2001-07-10

Berhane, Adolf Deneke (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S273000

Reexamination Certificate

active

06259238

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally related to voltage regulator circuits, and more particularly low quiescent current regulators.
BACKGROUND OF THE INVENTION
The “dropout voltage” of a voltage regulator equals the minimum input-to-output voltage differential for which the circuit can maintain output regulation. Low-dropout (LDO) voltage regulators generally have dropout voltages of a few tenths of a volt at full rated current. In order to achieve such low dropout voltages, the circuit must use a PNP or PMOS pass element.
FIG. 1
shows a simplified block diagram of a typical prior art PMOS LDO circuit
10
. The pass element is MOS transistor M
1
, which is driven by amplifier A
1
. The amplifier in turn receives the voltage generated by an internal voltage reference VR
1
, and the voltage produced by a voltage divider network R
1
-R
2
. The circuit
10
is connected so that the amplifier achieves equilibrium when the voltage on the tap T of the voltage divider equals the voltage generated by the reference VR
1
.
Many LDO applications require that the regulator consume little current to power its internal circuitry. This quiescent current typically equals 100 &mgr;A for a modern PMOS LDO, and this changes little regardless of output current. The conventional topology of
FIG. 1
can be extended to provide low-current operation, typically down to 10 &mgr;A. Lower currents require nonconventional circuit topologies.
The micropower LDO architecture contains multiple poles at relatively low frequencies, and therefore requires the insertion of compensating zeros to boost the phase, or otherwise the phase margin will deteriorate to the point that the circuit becomes unstable. These zeros are difficult to generate using integrated components because they must lie at relatively low frequencies (10-100 kHz), they must not use large amounts of die area, and they must not consume any current. There are two basic techniques that have been used to insert zeros in this type of LDO architecture:
1) Placing a resistor Resr in series with the load capacitor C
L
producing a zero at w=1/(R
esr
×C
L
). This can't make a low-frequency pole for a small capacitor value unless a large resistor R
esr
is used, which is undesirable. Since micropower architectures have low bandwidth, they require low-frequency poles and this isn't a good solution—by itself.
2) Place a capacitor C (not shown) across the upper resistor R
1
of the feedback divider; this produces a zero at w=1/(R
1
×C). This doesn't work well for small divider ratios because the pole-zero separation becomes too small.


REFERENCES:
patent: 4710728 (1987-12-01), Davis
patent: 4792745 (1988-12-01), Dobkin
patent: 4851953 (1989-07-01), O'Neill et al.
patent: 4902959 (1990-02-01), Brokaw
patent: 5672962 (1997-09-01), Sweeney
patent: 5686821 (1997-11-01), Brokaw

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