Broadcast video desynchronizer

Television – Synchronization – Phase locking regenerated subcarrier to color burst

Patent

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Details

348500, 348 7, 348 10, 375358, 375371, H04N 505

Patent

active

06133958&

DESCRIPTION:

BRIEF SUMMARY
This invention relates to the provision of television or video services on a synchronous network, and in particular to the desynchronisation of such services at a user station.


BACKGROUND OF THE INVENTION

The provision of 34 Mbits television services on the synchronous network requires stringent control of low frequency phase at the desynchroniser. As 34 M video codecs linearly encode the colour sub carrier of the PAL signal, any phase disturbances introduced by the synchronous transport (e.g. SDH) network propagate through the codec and into the reconstituted video. There are two bounding parameters that the video network providers consider to be important to deliver an acceptable quality of service to customers. First the phase transients in the bit stream must be such that the colour sub carrier, at 4.43 MHz will have no greater than a 0.1 Hz per second rate of change. Second, the delay budget in a telephony link must be no more than 100 microseconds. The final parameter of interest in bounding the desynchroniser system is that the network requires a minimum of 30 s to set up a connection. This is very much a worst case scenario, and more common switch times are in the order of up to 30 minutes and more. The most difficult problem is that of eliminating phase disturbances arising from the arrival of the video pointers which are used to bring the net flow of information back to the original input rate. A number of techniques have been proposed to address this problem, but none has been entirely successful.
A desynchroniser which uses the synchronous property of SONET to diminish the effect of pointer variations on an output clock phase is described by S. Say in Bellcore Standard T1X1.6/88-026, Jul. 25, 1988, pages 2 to 9.


SUMMARY OF THE INVENTION

According to one aspect of the invention there is provided an arrangement for desynchronising video signals broadcast over a synchronous network, the arrangement including means for demapping input video information, a feedback control loop incorporating a first-in-first-out (FIFO) buffer store into which the demapped video information bytes are written and from which said bytes are read, said store having a first wriite input for the demapped information, a second read input and an output, an amplifier coupled to the output of the buffer store, a tuneable oscillator adapted to provide a video line clock from the demapped video information and coupled to the output of the amplifier via a transfer function circuit, and an integrator coupled to the oscillator and to the read input of the FIFO buffer so as to close the feedback loop and so as to determine the fill depth of the FIFO buffer, said fill depth providing an error reference for the feedback control loop, there being means for controlling the oscillator frequency and for reading the video information from the store at a rate determined by the oscillator frequency such that the rate of information flow around the feedback control loop is substantially constant.
According to a further aspect of the invention there is provided a method for desynchronising video signals broadcast over a synchronous network incorporating a feedback control loop having a first-in-first-out (FIFO) buffer store having read and write inputs and into which received video bytes are written and from which said bytes are read, an amplifier coupled to the output of the buffer store, a tuneable oscillator adapted to provide a video line clock from the demapped video information and coupled to the output of the amplifier via a transfer function circuit, and an integrator coupled to the oscillator and to the read input of the FIFO buffer so as to close the feedback loop and so as to determine the fill depth of the FIFO buffer, the method including demapping said received video information, writing the demapped video information into the wriite input of said buffer store, providing an error reference signal for the feedback control loop from the fill depth of the FIFO buffer, and controlling the oscillator frequency and reading the vi

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Say, "A Synchronous Desynchronizer", Contribution To T1 Standards Project, Jul. 25, 1988, pp. 2-9.

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