Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-05-22
2004-03-30
Vincent, David (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395430
Reexamination Certificate
active
06714555
ABSTRACT:
The present invention relates to broadband telecommunications switches which operate to switch packets or cells of data from a plurality of input ports to a plurality of output ports. In particular, but not exclusively, the present invention relates to broadband telecommunications switches which operate in accordance with Asynchronous Transfer Mode (ATM) principles.
Telecommunications systems which communicate data at rates in the order of mega bits per second are known as broadband telecommunications systems. In order to effect communication of data at such high rates between a plurality of sources and a plurality of receivers, telecommunications systems are adapted to make optimum use of an amount of data communications bandwidth provided by a telecommunications network. To this end, broadband telecommunications systems operate to communicate data in a form of discrete packets or cells which carry a predetermined amount of information. An example of such a broadband telecommunications system is an Asynchronous Transfer Mode (ATM) telecommunications system, wherein data is conveyed in ATM cells. Each ATM cell comprises a predetermined quantity of data as well as a cell header, which contains a virtual channel identifier and a virtual path identifier which are used by nodes or switches of a telecommunications network to route the ATM cells between sources and receivers.
To achieve an efficient utilisation of a data communications bandwidth provided by a telecommunications network, telecommunications systems may further operate to provide a predetermined series of data transport media characterised by predefined data transmission parameters such as delay, integrity and cell rate. The telecommunications system is therefore arranged to provide a series of virtual communications paths, each of which is arranged to communicate data in accordance with the predetermined transmission parameters. Such communications paths are known as bearers, each of which is defined by the attributes of the data which it is to communicate. Hence, by selecting an appropriate bearer, a user of the telecommunications network is provided with a cost effective means for communicating broadband data in accordance with the type and attributes of data the user is generating.
Bearer types may include Constant Bit Rate (CBR) which may be delay and integrity critical. An example of a service carried by a CBR bearer is voice or speech data. Other bearer types include Variable Bit Rate (VBR) which is provided for data sensitive to losses and some tolerance to delay, and Available Bit Rate (ABR) which is loss sensitive but comparatively delay insensitive. There is also a data bearer type for data which is insensitive to both delay and integrity, which is known as Unspecified Bit Rate (UBR). CBR, ABR, VBR and UBR are defined for ATM in accordance with the ATM Forum.
In order to switch data received on an input port of a broadband telecommunications switch to a plurality of output ports, the broadband telecommunications switch must operate at a substantially higher rate than the rate at which data is received on the input port. To effect the switching operation, a core of the broadband telecommunications switch operates to interrogate packets of data received from an input port to determine which of the plurality of output ports the data packets should be sent, and routes the packets from the input port to the corresponding output port. If there are n output ports associated with a broadband telecommunications switch, then the core must operate at a rate of n multiplied by the bit rate or bandwidth associated with any input port, if no delay or loss of data is to be incurred in association with the switching operation. Furthermore, if there are n input ports, then the rate of processing of the switch core must be n
2
multiplied by the bit rate or bandwidth of receiving data on any one input port.
In order to reduce the processing rate required of the switch core, known ATM switches are provided with data buffers which are operatively associated with each of the input ports, and which operate to store ATM cells at the input port until an output port to which they are to be switched has sufficient capacity to receive these ATM cells. This allows for a substantial reduction in the processing rate of the switch core. An example of a known ATM switch is disclosed in granted UK patent number 2272820B.
As with the input ports, a data rate or bandwidth limit for communicating data is associated with each of the output ports. Typically, but not exclusively, the data rate of the input ports is equal to the data rate of the output ports which are also equal to each other. As such, communications bandwidth associated with the output port is bandwidth limited, so that a technical problem exists in arranging for data packets received on the input port to be switched between the output ports whilst accommodating the bandwidth limit associated with each output port, and insuring that no data packet is lost in communication between the input ports and the output ports.
The technical problem of switching data packets from a plurality of input ports to a plurality of output ports, which output ports are bandwidth limited, is addressed by the present invention.
According to the present invention there is provided a broadband telecommunications switch for switching packets of data received on a plurality of input ports to a plurality of bandwidth limited output ports, said switch comprising for each input port a control processor which operates to communicate request data for each of a plurality of switching periods to each of a plurality of bandwidth allocators operatively associated with said output ports, which request data is representative of a request for communications bandwidth from said output ports sufficient to accommodate packets of data received at said input ports during a corresponding switching period, wherein each of said bandwidth allocators responds to said request data by generating bandwidth allocation data appertaining to an allocation of a share of the bandwidth of the output port to the input port and communicates bandwidth allocation data to each of said input ports, which share of bandwidth said input port uses to switch said data packets from said input ports to said output ports.
The request data may represent a number of data packets received at the input port during the corresponding switching period.
Each of said input ports may further include for each output port a data store for buffering data packets received at the input port before being communicated to a respective output port via said switch core. The control processor associated with each input port may operate to generate request data in accordance with a number of data packets present in said data stores for communication to said output ports.
Switching of data packets between input ports and the output ports of a broadband telecommunications switch represents a task of some considerable complexity. This is because there is not only a wide variation in data rates of data arriving at the input ports of the switch, but also a plurality of bearer types with different integrity and delay sensitivities. By arranging for a control processor associated with each input port to periodically transmit to each of the output ports request data representative of a bandwidth requirement from the corresponding output port sufficient to egress the data received at the input port for a given switching period, the allocation of the bandwidth of the output ports to the input ports may be effected in a quasi synchronous manner, the effect of which is to substantially reduce the complexity of the switch compared to a switch where bandwidth allocation is executed asynchronously.
Although allocation of the bandwidth of the output ports is effected in a quasi synchronous manner, switching of data packets is effected asynchronously.
The switching period is a period of time for which the bandwidth allocation of the output ports to each of the input ports is substantiall
Excell Michael John
Hayter Andrew Timothy
Phillips Ian Lesseter
Urry Christopher Paul
Crowell & Moring LLP
Roke Manor Research Limited
Vincent David
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