Broadband digital phase aligner

Details Broadband digital phase aligner Broadband digital phase aligner

1993-04-16

1994-01-11

Kuntz, Curtis

Pulse or digital communications

Spread spectrum

Direct sequence

328 55, H04L 702

Patent

active

052788733

ABSTRACT:
Automatic dynamic phase alignment of digital data, skewed with respect to a local clock, is obtained over a wide range of skew and skew frequencies. The system includes (i) an edge detector (52) containing predetermined delays (e.g., D1, D2, D3), (ii) delay registers (e.g., 72, 76, 84, 86), and (iii) a controller (54) for deciding when un-delayed and delayed data D0, D1, D2, D3 have transitions (102-138) which bracket corresponding clock transitions (100, 110, 120, 130) and regulating a subsequent two-stream parallel (e.g., bi-phase) register-multiplexer (56). The controller selects from the register-multiplexer (56), whichever of in-phase data D or delayed data DD has its transition spaced away from the clock transition by at least one delay D1, D2, or D3.

REFERENCES:
patent: 4756011 (1988-07-01), Cordell
patent: 4821296 (1989-04-01), Cordell
patent: 4841551 (1989-06-01), Avaneas
patent: 4949361 (1990-08-01), Jackson
"A 45-Mbit/s CMOS VLSI Digital Phase Aligner", by Rober R. Cordell, IEEE Journal of Solid-State Circuit, vol. 23, No. 2, Apr. 1988 pp. 323-328.

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