Bridge circuit for preventing data incoherency by holding off pr

Details Bridge circuit for preventing data incoherency by holding off pr Bridge circuit for preventing data incoherency by holding off pr

1995-10-16

1997-11-25

Harvey, Jack B.

395308, G06F 1300

Patent

active

056922000

ABSTRACT:
A bridge circuit for holding off primary interrupts signaling the completion of a block data transfer from a second bus to a system bus until the data has cleared the bridge circuit. The bridge circuit includes an interrupt control circuit for receiving up to seven primary interrupt signals corresponding to seven sets of bus grant-request lines on a second bus. Each bus grant-request set is assigned a data FIFO for synchronizing the transfer of data from the second bus to a system bus. The interrupt control circuit provides an interrupt to the system bus which corresponds to the primary interrupt only after the associated data FIFO is empty, thereby preventing data coherency problems in system memory.

REFERENCES:
patent: 4864496 (1989-09-01), Triolo et al.
patent: 4935894 (1990-06-01), Ternes et al.
patent: 5414814 (1995-05-01), McKim
patent: 5535341 (1996-07-01), Shah et al.
patent: 5560019 (1996-09-01), Narad

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