Patent
1983-12-05
1986-02-25
Clawson, Jr., Joseph E.
357 20, H01L 2906
Patent
active
045730660
ABSTRACT:
In order to increase the breakdown voltage of a reverse-biased p-n junction of a semiconductor device, at least three annular regions which extend around the active device region are located within the spread of a depletion layer from the junction. At least one inner annular region is wider than outer annular regions, and this increased width of the inner region or regions reduces peak electrostatic fields found to occur at the bottom outer corners of the active device region and inner annular regions. The spacing of the annular regions increases with remoteness from the active device region, although at least two inner annular regions may have the same spacing as that of the innermost annular region from the active device region. A group of annular regions may have the same width as each other in the group.
REFERENCES:
patent: 3391287 (1968-07-01), Kao et al.
patent: 3971061 (1976-07-01), Matsushita et al.
patent: 4003072 (1977-01-01), Matsushita et al.
T. Matsushita et al., "New Semi. Devices of Ultra-High Breakdown Volt," 1973 IEDM, pp. 109-110, Washington, D.C.
Y. Kao et al., "High-Voltage Planar P-N Jcns.," Proc. IEEE, vol. 55 #8, Aug. 1967, pp. 1409-1414.
Biren Steven R.
Clawson Jr. Joseph E.
Mayer Robert T.
U.S. Philips Corporation
LandOfFree
Breakdown voltage increasing device with multiple floating annul does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Breakdown voltage increasing device with multiple floating annul, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Breakdown voltage increasing device with multiple floating annul will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1014614