Breakdown-free negative level shifter

Details Breakdown-free negative level shifter Breakdown-free negative level shifter

2001-09-24

2002-11-19

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S081000

Reexamination Certificate

active

06483366

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90102336, filed on Feb. 5, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a negative level shifter. More particularly, the present invention relates to a field breakdown-free negative level shifter.
2. Description of Related Art
FIG. 1
is a circuit diagram of a conventional negative level shifter. As shown in
FIG. 1
, the negative level shifter consists of a pair of PMOS transistors
10
and
12
and a pair of NMOS transistors
14
and
16
. An input voltage is fed to a point A of the circuit. The source terminal of the PMOS transistor
10
and the gate terminal of the PMOS transistor
12
are connected to point A. The gate terminal of the PMOS transistor
10
is connected to a ground voltage Vss. The source terminal of the PMOS transistor
12
is connected to a supply voltage Vdd. The drain terminal of the PMOS transistor
10
is connected to both the drain terminal of the NMOS transistor
14
and the gate terminal of the NMOS transistor
16
. In addition, the drain terminal of the PMOS transistor
12
is connected to both the gate terminal of the NMOS transistor
14
and the drain terminal of the NMOS transistor
16
. The source terminal of the NMOS transistors
14
and
16
are connected together for receiving a negative voltage (for example, −5V or −10V).
In operation, an input voltage within the range 3.3V to 0V is applied to the input terminal at point A. When 3.3V are applied to point A, the PMOS transistor
10
having its gate terminal connected to a ground voltage Vss is conductive. The PMOS transistor
12
is disabled. Since the PMOS transistor
10
is conductive, 3.3V are applied to point B, leading to the conduction of the NMOS transistor
16
. Hence, the negative voltage connected to the source terminal of the NMOS transistor
16
is transmitted to point C as an output voltage and the NMOS transistor
14
, whose gate terminal is connected to point C, is disabled. Conversely, when 0V is applied to point A, the PMOS transistor
10
is disabled. However, the PMOS transistor
12
is conductive so that a supply voltage (for example, 3.3V) is directly transmitted to point C. In the meantime, the NMOS transistor
14
is conductive and the negative voltage at the source terminal of the NMOS transistor
14
is transmitted to point B. Hence, the NMOS transistor
16
is disabled.
According to the aforementioned operation, a negative shifting of −5V or −10V is obtained. One critical problem for this type of circuit is field breakdown because most circuit breakdown at a change in field voltage smaller than 12V. Therefore, when an input voltage change from 3.3V to 0V or vice versa occurs, if the desired negative voltage is large, such as −10V, output voltage must vary between −10V to 3.3V. The 13.3V voltage fluctuation at the output terminal exceeds the greatest permitted breakdown voltage.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a field breakdown free negative level shifting circuit for preventing too much output voltage variation when the output negative voltage desired is large.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a two-stage negative level shifting circuit for preventing field breakdown. The two-stage negative level shifting circuit includes a first stage circuit having a first voltage distributor and a first driver and a second stage circuit having a second voltage distributor and a second driver. The first voltage distributor converts an input voltage shifting between a ground voltage and a positive voltage to a corresponding first distributor voltage or output voltage shifting between a first negative voltage and a positive voltage. The first driver is connected to the first voltage distributor for converting the first distributor voltage shifting between the positive voltage and the first negative voltage into corresponding first driving voltage or output voltage shifting between the first negative voltage and the ground voltage. The second voltage distributor is connected to the first driver for converting the first driving voltage shifting between the ground voltage and the first negative voltage into a corresponding second distributor voltage or output voltage shifting between a second negative voltage and the ground voltage. The second driver is connected to the second voltage distributor for converting the second distributor voltage shifting between the second negative voltage and the ground voltage into a corresponding second driving voltage shifting between the ground voltage and the second negative voltage. The absolute value of the second negative voltage is greater than the first negative voltage.
The first voltage distributor includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor and a second NMOS transistor. The source terminal of the PMOS transistor receives the input voltage and the gate terminal of the PMOS transistor receives the ground voltage. The drain terminal of the first NMOS transistor connects with the drain terminal of the PMOS transistor and the source terminal of the first NMOS transistor receives the first negative voltage. The source terminal of the second PMOS transistor receives a supply voltage and the gate terminal of the second PMOS transistor receives the input voltage. The drain terminal of the second PMOS transistor serves as an output for the first distributor voltage and connects with the gate terminal of the first NMOS transistor. The drain terminal of the second NMOS transistor connects with the drain terminal of the second PMOS transistor and the gate terminal of the second NMOS transistor connects with the drain terminal of the first NMOS transistor. The source terminal of the second NMOS transistor receives the first negative voltage. The supply voltage is a positive voltage having a magnitude of 3.3V and the first negative voltage is −5V, for example.
The first driver includes a third PMOS transistor and a third NMOS transistor. The source terminal of the third PMOS transistor receives the ground voltage and the gate terminal of the third PMOS transistor receives the first distributor voltage. The drain terminal of the third NMOS transistor connects with the drain terminal of the third PMOS transistor to serve as an output for the first driver voltage. The gate terminal of the third NMOS transistor receives the first distributor voltage and the source terminal of the third NMOS transistor receives the first negative voltage.
The second voltage distributor includes a fourth PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor and a fifth NMOS transistor. The source terminal of the fourth PMOS transistor receives the first driving voltage and the gate terminal of the fourth PMOS transistor receives the first negative voltage. The drain terminal of the fourth NMOS transistor connects with the drain terminal of the fourth PMOS transistor and the source terminal of the fourth NMOS transistor receives the second negative voltage. The source terminal of the fifth PMOS transistor receives the ground voltage and the gate terminal of the fifth PMOS transistor receives the first driving voltage. The drain terminal of the fifth PMOS transistor serves as an output for the second distributor voltage and connects with the gate terminal of the fourth NMOS transistor. The drain terminal of the fifth NMOS transistor connects with the drain terminal of the fifth PMOS transistor and the gate terminal of the fifth NMOS transistor connects with the drain terminal of the fourth NMOS transistor. The source terminal of the fifth NMOS transistor receives the second negative voltage. The second negative voltage is −10V, for example.
The second driver includes a sixth PMOS transistor and a sixth NMOS transistor. The source terminal of the s

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