Boots – shoes – and leggings
Patent
1994-10-28
1998-05-05
Louis-Jacques, Jacques H.
Boots, shoes, and leggings
364489, 364578, 364DIG1, G06F 1750
Patent
active
057484864
ABSTRACT:
A breadth-first manipulation of reduced, ordered binary decision diagram representation of a logic circuit eliminates page access time bottlenecks encountered when obtaining nodes from secondary memory to primary memory by providing an orderly page access arrangement. The pointer to a node is the address at which the node is located in memory, from which address the memory block at which the node is located is determined. A look-up table is used to convert the memory block information into a variable index indicative of the level at which the node is located. The queue of ITE (if.sub.-- then.sub.-- else) requests is maintained on a per level basis.
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Ashar Pranav
Cheong Chao
Feig Philip J.
Louis-Jacques Jacques H.
NEC USA Inc.
Phan Thai
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