Branching system for return from subroutine using target address

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395800, 39542103, 3642557, 3642614, 3649555, 3649383, 364DIG1, 364DIG2, G06F 942

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054540879

ABSTRACT:
An address of a branch instruction, a branch target address thereof, and a type thereof are stored as branch history information in a branch instruction buffer. In addition, a return address for a return from a subroutine is retained in a return buffer. A look-up operation is conducted through the buffer by using the pre-fetch address such that when a hit occurs, a branch target address is output from the buffer depending on a branch instruction type. Consequently, the branch processing is achieved at a high speed. Particularly, the processing speed of an unconditional branch instruction containing a return instruction is increased.

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patent: 4884244 (1989-11-01), Brewer
patent: 4984154 (1991-01-01), Hanatami et al.
patent: 4991080 (1991-02-01), Emma et al.
patent: 5101341 (1992-03-01), Circello et al.
patent: 5276882 (1994-01-01), Emma et al.
patent: 5313634 (1994-05-01), Eickemeyer
IBM Technical Disclosure Bulletin, "Subroutine call/return stack," vol. 30, No. 11, pp. 221-225, Apr. 1988.

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