Boots – shoes – and leggings
Patent
1985-06-25
1990-12-11
Chan, Eddie P.
Boots, shoes, and leggings
3642318, 3642631, 3642613, 3642617, 364259, 3642592, 364258, 3642581, 3642716, G06F 700
Patent
active
049774964
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
CROSS REFERENCES TO RELATED APPLICATIONS
This application is related to U.S. applications having Ser. Nos. 758,664; 758,665 and 755,321.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a branching control system, particularly a branching control system in a data processing unit having pipeline control where the amount of processing necessary for cancellation of one branch when successful branching has occurred is reduced by generating a branching address and fetching an instruction at a branch-to address while executing condition testing of the branching instruction.
2. Description of the Related Art
In recent large scale computer systems, it has become common for data to be processed quickly using a pipeline type system. High speed processing utilizing the characteristics of a pipeline can be used for processing ordinary instructions that flow sequentially. However, with respect to branching instructions, the successive instructions already fetched and residing in the pipeline may have to be invalidated when the branching conditions are finally determined, generating lost-cycles. Particularly, for data base processing operations or the online data processing operations which are the data processing operations receiving increased attention, the ratio of executing branching instructions to non-branching instruction is large and the lost-cycles generated in the pipeline system are high in number and therefore a pipeline processing system which can reduce the number of lost-cycles is greatly desired.
Operations by prior art systems, when an index high branching (hereinafter referred to as BXH) instruction or the index low equal branching (hereinafter referred to as BXLE) instruction are executed in the data processing system which executes instructions in a pipeline, are explained below. The BXH instruction and BXLE instruction are of the register storage (RS) type as shown in FIG. 1, where OP is the operation code area; R1, R3, B2 are register designation areas. The contents of general purpose register R1 is the first operand, the contents of general purpose register R3 is the third operand and the value obtained by adding a displacement value of D2 to the contents of general purpose register B2 becomes the second operand.
The BXH instruction branches to the address indicated by the second operand when an increment of the third operand is added to said first operand (hereinafter referred to as an index) and the result is larger than a comparison number designated by the contents of the R3 register area. Even when the branch is not taken, the content of the first operand is updated by the increment. The increment is the content (third operand) of the general purpose register designated by R3 as mentioned above. The comparison number is in the next general purpose register having an odd number, for example when R3 indicates an even numbered register, the comparison number is the content of general purpose register indicated by the content of R3+1, and when R3 indicates an odd numbered register, the comparison number is the content of the general purpose register indicated by R3.
It is also possible that the general purpose register includes the same comparison number as the first operand and in this situation an initial value before adding the increment is used as the comparison number.
The BXLE instruction is the same as said BXH instruction, except that the conditions for branching are inverted and branching is carried out when the index is smaller than or equal to the comparison number.
The pipeline operations in the prior art system for executing the BXH and BXLE instructions are explained with reference to FIG. 2. In FIG. 2. P1, P2, P3, P4, P5 and P6 are pipeline stages and the general operations thereof are as follows: registers; memory access request; conversion buffer; registers.
Execution of branching instructions using a pipeline is generally performed in such a manner that one instruction can develop one or a plurality of flows, the original
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Onishi Katsumi
Ono Yuto
Chan Eddie P.
Fujitsu Limited
Rudolph Rebecca L.
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