Branched-spiral wafer-scale integrated circuit

Details Branched-spiral wafer-scale integrated circuit Branched-spiral wafer-scale integrated circuit

1982-11-12

1985-05-21

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

045190356

ABSTRACT:
A wafer-scale integrated circuit has a plurality of data-processing cells disposed on a semiconductor wafer together with a port for providing communications with a controller. A branched spiral of inter-coupled working cells is grown starting at the port by testing cells and incorporating them into the branched spiral if found to be working, otherwise selecting alternative cells for testing. The growth of the branched spiral is such as to allow for the incorporation of cells trapped in cul-de-sacs. Each cell is operable to receive a unique cell name from the controller and is thereafter operable to respond to commands from the controller bearing its unique cell name to couple firstly to one neighbor and secondly, at any time thereafter, to couple to a further neighboring cell. The controller is provided with means for maintaining records of successful interconnections for later use.

REFERENCES:
patent: 3794983 (1974-02-01), Sahin
patent: 3913072 (1975-10-01), Catt
patent: 3961251 (1976-06-01), Hurley
patent: 4037205 (1977-07-01), Edelberg
patent: 4038648 (1977-07-01), Chesley
patent: 4060713 (1977-11-01), Golay
patent: 4191996 (1980-03-01), Chesley
patent: 4215401 (1980-07-01), Holsztynski
R. C. Aubusson and I. Catt, "Wafer-Scale Integration--A Fault-Tolerant Procedure", IEEE Jo. of Solid State CKts, vol. SC-13, No. 3, Jun. 1978, pp. 339-344.
F. B. Manning, "An Approach to Highly Integrated, Computer-Maintained Cellular Arrays", IEEE Transactions on Computers, vol. C-26, No. 6, Jun. 1977, pp. 536-552.

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