Branched labyrinth wafer-scale integrated circuit

Details Branched labyrinth wafer-scale integrated circuit Branched labyrinth wafer-scale integrated circuit

1981-11-17

1984-09-11

Atkinson, Charles E.

Excavating

371 11, G01R 3128

Patent

active

044714831

ABSTRACT:
A memory system includes an integrated circuit comprising a plurality of testably interconnectable cells in a tessellation on a semiconducting wafer. A controller for acting as an interface between the wafer and some host system is coupled to the wafer via a port formed by the omission of one of the cells from the tessellation. Each cell comprises plural-bit data storage registers each having an associated single-bit access register and an associated single-bit control register. During a growth phase a state machine co-operates with global signals and test data from the controller to operate data-testing and inter-register coupling logic to form a branched-labyrinth of tested cells characterized by rapid growth and efficient incorporation of functional cells. After growth data is transferred between the chain of data storage registers and the chain of access registers so formed dependently upon the contents of an associated chain of control registers. A rapid retrieval associative memory facility is incorporated allowing named data to be withdrawn on presentation of a maskable naming word to the control register chain.

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