Branch target buffer for dynamically predicting branch instructi

Details Branch target buffer for dynamically predicting branch instructi Branch target buffer for dynamically predicting branch instructi

1995-07-31

1996-12-10

Treat, William M.

Boots, shoes, and leggings

3642613, 364DIG1, 364DIG2, 395587, G06F 900

Patent

active

055840019

ABSTRACT:
A branch prediction mechanism that maintains both speculative history and actual history for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history plus the "history" of recent branch predictions for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set, this indicates that there is speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history.

REFERENCES:
patent: 4477872 (1984-10-01), Losq et al.
patent: 4679141 (1987-07-01), Pomerene et al.
patent: 4991080 (1991-02-01), Emma et al.
patent: 5142634 (1992-08-01), Fite et al.
patent: 5168557 (1992-12-01), Shibuya
patent: 5210831 (1993-05-01), Emma et al.
patent: 5226130 (1993-07-01), Fauok et al.
patent: 5265213 (1993-11-01), Weiser et al.
patent: 5442756 (1995-08-01), Grochowski et al.
patent: 5488730 (1996-01-01), Brown, III et al.
Superstar Microprocessor Design; author: Mike Johnson; Published by Prentice Hall, Inc., New Jersey; 1991; pp. 57-85 and 261-272.
Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation, Pan et al. pp. 76-84.
Future Trends in Microprocessors out of Order Exceution, Speculative Branching and their CISC Performance Potential Peleg et al, IEEE publication pp. 263-266.
IEEE Micro, Published Jun., 1991, pp. 10-13, and 63-73, Authors: Val Popescu, et al., Entitled: The Metaflow Architecture.
"Alternative Implementations of Two-Level Adaptive Branch Prediction", by Tse-Yu Yeh & Yale N. Patt (pp. 124-134) published 1992 by ACM.
"Branch Prediction Strategies and Branch Target Buffer Design", by Johnny K. F. Lee & Alan J. Smith (pp. 6-22) published 1984 by Computer.
"Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation", by Shien-Tai Pan, Kimming So & Joseph T. Rahmeh (pp. 76-84) published 1992 by ACM.
"Two-Level Adaptive Training Branch Prediction", by Tse-Yu Yeh & Yale N. Patt (pp. 51-61) published 1991 by ACM.

Affiliated with

Also associated with

Rating

Branch target buffer for dynamically predicting branch instructi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Branch target buffer for dynamically predicting branch instructi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Branch target buffer for dynamically predicting branch instructi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-431753