Branch processing unit with target cache storing history for pre

Details Branch processing unit with target cache storing history for pre Branch processing unit with target cache storing history for pre

1996-02-26

1998-03-24

Lall, Parshotam S.

395587, G06F 938

Patent

active

057322538

ABSTRACT:
A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU implements a branch prediction scheme using a target cache and a separate history cache. The target cache stores target addressing information and history information for predicted taken branches. The history cache stores history information only for predicted not-taken branches. The exemplary embodiment uses a two-bit prediction algorithm such that the target cache and the history cache need only story a single history bit (to differentiate between strong and weak states of respectively predicted taken and not-taken branches).

REFERENCES:
patent: 5353421 (1994-10-01), Emma et al.
patent: 5454117 (1995-09-01), Puziol et al.

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