Branch processing unit with a far target cache accessed by indir

Details Branch processing unit with a far target cache accessed by indir Branch processing unit with a far target cache accessed by indir

1996-02-26

1998-04-14

Lall, Parshotam S.

395414, G06F 938

Patent

active

057404160

ABSTRACT:
A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. In one embodiment, the BPU includes a target cache and a separate far target cache--the far target cache stores limits and mode bits for far targets stored in the target cache. For each far COF entry in the target cache, an FTC index field stores an index pointing to the corresponding entry in the far target cache. For far COFs that hit in the target cache, the target cache outputs corresponding far target addressing information and the associated FTC index to indirectly access the far target cache to obtain the associated segment limit information.

REFERENCES:
patent: 4679141 (1987-07-01), Pomerene et al.
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5608886 (1997-03-01), Blomgren et al.

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