Branch prediction unit for high-performance processor

Details Branch prediction unit for high-performance processor Branch prediction unit for high-performance processor

1993-07-01

1995-02-28

Coleman, Eric

Boots, shoes, and leggings

3642613, 3642615, 3642617, 3642631, 364DIG1, G06F 926

Patent

active

053945298

ABSTRACT:
A pipelined CPU executes instructions of variable length, and references memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical aglorithm to predict which way the next occurrence of this branch will go, based upon the history table. The branch history table stores in each entry a number of bits for each branch address, each bits indicating "taken" or "not-taken" for one occurrence of the branch. The table is indexed by branch address. A register stores the empirical aglorithm, and upon occurrence of a branch its history is fetched from the table and used to select a location in the register containing a prediction for this particular pattern of branch history.

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patent: 4984154 (1991-01-01), Hanatani
patent: 5228131 (1993-07-01), Ueda
Troiani et al., "The VAX 8600 I Box, A Pipelined Implentation of the VAX Architecture", Digital Technical Journal, Aug. 1985, pp. 24-42.
Smith, "A study of Branch Prediction Strategies", 8th Ann. Symposium on Computer Architecture, Minneapolis, Minn., May 12-14 1981, pp. 135-114
Losq, "Generalized History Table for Branch Prediction", IBM Tech. Discl. Bull., Jun. 1982, pp. 99-101.
Rao, "Technique for Minimizing Branch Delay Due to Incorrect Branch History Table Predictions", IBM Tech. Discl. Bull., Jun. 1982, pp. 97-98.
Parks et al., "Target Prefetch Table", IBM Tech. Discl. Bull., Sep. 1982, pp. 2128-2129.

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