Branch prediction table having pointers identifying other branch

Details Branch prediction table having pointers identifying other branch Branch prediction table having pointers identifying other branch

1995-12-22

1998-09-29

Ellis, Richard L.

G06F 932

Patent

active

058157000

ABSTRACT:
A branch prediction system is described for use within a microprocessor having an instruction cache capable of storing two or more instructions per cache line. Each entry of a branch prediction table (BPT) includes a value identifying whether at least one other instruction within a common cache line contains a branch. The value is referred to herein as a multiple-B bit value. The multiple-B bit value is examined by branch prediction logic while one branch prediction is being performed to determine whether a second branch prediction can be initiated for another branch within the same cache line. In one implementation, the multiple-B bit of one BPT entry is examined following a hit. A branch prediction for the entry generating a hit is initiated. Simultaneously, the BPT is reaccessed to search for an entry corresponding to another instruction within the same cache line if the multiple-B bit for the first entry was set. If the second entry is found, a secondary branch prediction is initiated. Eventually, the first branch prediction is output. If the first branch prediction is Not Taken, then the second branch prediction is output during the next clock cycle. If the first branch prediction is Taken, then the second branch prediction may be aborted as it is not needed. Method and apparatus embodiments of the invention are described.

REFERENCES:
patent: 4943908 (1990-07-01), Emma et al.
patent: 4991080 (1991-02-01), Emma et al.
Sonh et al, An Implementation of Branch Target Buffer for High Performance Applications, IEEE Tencon. IEEE Region 10 International Conference on Microelectronics and VLSI, pp. 492-495, 1995.

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