Branch prediction system using limited branch target buffer upda

Details Branch prediction system using limited branch target buffer upda Branch prediction system using limited branch target buffer upda

1995-12-27

1998-04-07

Lall, Parshotam S.

395586, 395587, G06F 922

Patent

active

057375909

ABSTRACT:
In a BTB, a lower part (ten-odd bits) of a branch target address obtained when a branch target generator executes a branch instruction is entered or updated as a prediction index. A linker links a prediction index signal (S1) read from the BTB with a PC output signal (S.sub.A) indicating an upper part (several bits) of a branch instruction address to generate and output a predicted target address signal (S2) in a fetch stage. A comparator compares the branch target address signal (S.sub.C) with the predicted target address signal (S2) to output a signal (S4) indicating whether they agree or not. A branch-prediction hit checking unit checks whether the branch prediction hits or misses by a result of a comparison between an execution result signal (S5) and a predicted direction signal (S3) and a result given by the signal (S4). Thus, a branch prediction system using the BTB enables reduction in volume of a BTB entry by half.

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