Branch prediction system for superscalar processor

Details Branch prediction system for superscalar processor Branch prediction system for superscalar processor

1997-03-13

1998-11-10

Harrell, Robert B.

G06F 942

Patent

active

058357548

ABSTRACT:
Each entry of BTBs (11 and 21) stores branch prediction information on a branch instruction including a 2-bit offset which indicates a location at which the branch instruction is stored in a cache block. The BTBs (11 and 21) simultaneously output the branch prediction informations stored in the entries specified by an index of an executable instruction address in an address fetch unit (1) as the first and second retrieval branch prediction informations, respectively. A selection circuit (2) determines a next program counter value (PC') on the basis of outputs of tag detection circuits (12 and 22), outputs of PC detection circuits (13 and 23), a tag in the address fetch unit (1), a program counter value (PC) and the first and second retrieval branch prediction informations.

REFERENCES:
patent: 5414822 (1995-05-01), Saito et al.
J. L. Hennessy et al, "Computer Architecture A Quantitative Approach", pp. 306-315.
B. Calder et al, "Next Cache Line and Set Prediction", pp. 287-296.

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