Patent
1997-11-20
1999-06-22
Lall, Parshotam S.
395394, G06F 938
Patent
active
059151102
ABSTRACT:
A reorder buffer for a microprocessor comprising a control unit, an instruction storage, and future file. The future file has storage locations associated with each register implemented in the microprocessor. The future file is configured to store a reorder buffer tag that corresponds to the last instruction, in program order, stored within the instruction storage that has a destination operand corresponding to the register associated with said storage location. The future file is further configured to store instruction results. The control unit is configured to read a particular reorder buffer tag from the future file that corresponds to a completed instruction and to compare the particular reorder buffer tag with the completed instruction's result tag. If the two tags compare equal, the control unit is configured to write any result data corresponding to the completed instruction into the future file. This advantageously reduces the number of comparators needed to maintain the future file. The future file is also configured to improve branch misprediction recovery speed by examining each entry in said instruction storage for a valid destination starting with the mispredicted branch instruction. This configuration advantageously allows older instructions in the instruction storage to be retired while the future file is being recovered, thereby reducing the number of instructions the control unit must process to recover the future file.
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Tran Thang M.
Witt David B.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Lall Parshotam S.
Merkel Lawrence J.
Vu Viet
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