Branch metric computer for a Viterbi decoder of a punctured and

Details Branch metric computer for a Viterbi decoder of a punctured and Branch metric computer for a Viterbi decoder of a punctured and

1994-11-18

1996-03-05

Tse, Young T.

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

375262, 371 378, 371 43, H03M 1312

Patent

active

054974011

ABSTRACT:
A branch metric computer for the Viterbi decoder of a convolutional decoder primarily intended for use in a multi-channel compressed-digital television receiver capable of receiving FEC data transmitted over satellite, terrestrial and transmission channels. The branch metric computer employs a RAM, having an effective depth of 2.sup.x storage locations and an effective storage-location width of 16 m, which is preloaded with two selectively programmed I and two selectively programmed Q lookup tables, wherein each table entry is made up of four m-bit values,. The RAM is designed to operate with either QPSK punctured-coded I and Q signal inputs or any one of a plurality of different PAM or QAM higher alphabet or an 8-PSK pragmatic trellis-coded 2.sup.x -bit I and 2.sup.x -bit Q signal inputs to the convolutional decoder that are forwarded as signal inputs to the RAM for controlling the particular I and Q lookup-table entries read out from the RAM. The branch metric computer further comprises (1) a group of eight Manhattan-distance metric computing summers organized into first and second sets of four summers for adding certain combinations of the four m-bit I and Q lookup-table entries read out from the RAM and (2) a network including four comparators with each of them forwarding to the Viterbi decoder the lesser sum output from corresponding ones of the summers of the first and second sets.

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Preliminary Data Bulletin for the Q1875 Trellis Decoder, Qualcomm Incorporated, VLSI Products Division, San Diego, Calif.
"Development of Variable Rate Viterbi Decoder and its Performance Characteristics", Proceedings of the 6th ICDSC Conference, Phoenix, Arizona, 1983, pp. XII-24-XII-31.
"A 25 MHz Viterbi FEC Codec" by Kerr et al., IEEE 1990 Custom Integrated Circuits Conference, pp. 13.6.1-13.6.5.
"Practical Coding for QAM Transmission of HDTV" by Heegard et al., IEEE Journal on Selected Areas in Communications, Jan. 1993, pp. 111-118.
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"45 Mbps Viterbi Decoder, STEL-2060", Stanford Telecommunications, Sunnyvale, Calif., 1992, 1993, pp. 1-15.

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