Branch loop performance enhancement

Details Branch loop performance enhancement Branch loop performance enhancement

2011-06-14

2011-06-14

Fennema, Robert (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction fetching

Prefetching

Reexamination Certificate

active

07962724

ABSTRACT:
A system and method for management of resource allocation for speculative fetched instructions following small backward branch instructions. An instruction fetch unit speculatively prefetches a memory line for each fetched memory line. Each memory line may have a small backward branch instruction, which is a backward branch instruction that has a target instruction within the same memory line. For each fetched memory line, the instruction fetch unit determines if a small backward branch instruction exists among the instructions within the memory line. If a small backward branch instruction is found and predicted taken, then the instruction fetch unit inhibits the speculative prefetch for that particular thread. The speculative prefetch may resume for that thread after the branch loop is completed. System resources may be better allocated during the iterations of the small backward branch loop.

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