Branch address calculating system for branch instructions

Details Branch address calculating system for branch instructions Branch address calculating system for branch instructions

1989-08-08

1992-02-11

Lee, Thomas C.

Boots, shoes, and leggings

3642318, 3642613, 364260, 3642598, 364358, 36493143, 364938, 36494834, 364DIG1, 364DIG2, G06F 932, G06F 928

Patent

active

050880306

ABSTRACT:
In the conventional branch address calculator for an advance control processor, when a branch instruction reaches the execution step, a decision is first made as to whether the branch instruction is conditional or non-conditional, and then a target branch address (logical address) is calculated before the branch instruction is executed, so that the processing speed is slow. To increase the processing speed, a target branch address is previously calculated before a branch instruction reaches the execution step. Since the branch instruction can be executed immediately after the condition of the branch instruction has been decided, it is possible to eliminate the time required to calculate the target branch address after the instruction has reached the execution step.

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IBM Technical Disclosure Bulletin, vol. 24, No. 1A, Jun. 1981; "Address Generate Interlock Avoidance for Branch Instructions in a Branch-History-Table Processor".

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