BPSK encoder circuit

Details BPSK encoder circuit BPSK encoder circuit

1999-05-04

2002-07-23

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Transmitters

Angle modulation

C375S279000, C375S355000, C332S104000

Reexamination Certificate

active

06424682

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of data encoding, and, in particular, to a BPSK (binary phase shift keying) encoding circuit.
BACKGROUND OF THE INVENTION
The transfer of binary data by carrier phase shifts, commonly known as binary phase shift keying (BPSK), is a well-known technique and an alternative to amplitude modulation or frequency modulation data transfer techniques. Furthermore, it is common for these various techniques to be combined, for example, a sub-carrier modulated by phase-shift keying used as a signal for the amplitude modulation or the frequency modulation of a main carrier.
Conventionally, as shown in
FIG. 1
, a BPSK encoder
1
comprises an encoding circuit
2
for receiving an input signal Sin to be encoded. The encoding circuit
2
also receives a carrier signal C
1
as well as a sampling signal C
2
having a frequency at least equal to twice the frequency of the carrier C
1
. A circuit
3
for receiving the carrier C
1
delivers the sampling signal C
2
to the encoding circuit
2
. The encoding circuit
2
delivers an output signal Sout encoded by phase shifts.
Specifically, exemplary signals C
1
, Sin and Sout are shown in
FIGS. 2A
,
2
B,
2
C. The output signal Sout resembles that of the carrier C
1
but has phase shifts
4
,
5
after each change in the logic value of the input signal Sin to be encoded. Phase shifts of this kind are synchronized and expressed by the fact that, during a half period, the signal Sout preserves the logic value that is presented during the preceding half-period, instead of changing its value.
Although this encoding technique is advantageous, especially because of a high signal-to-noise ratio and great ease of decoding, the standard BPSK encoders are complex to make. In particular, the circuit
3
delivering the sampling signal C
2
is conventionally comprised of a phase locked loop (PLL) with a certain complexity that is more difficult to implement than a purely logic circuit.
BRIEF SUMMARY OF THE INVENTION
Thus, it is an object of the present invention to provide a BPSK encoder that is efficient and simple to make at a low cost. Another object of the present invention is to provide for a BPSK encoder made exclusively out of standard logic gates that can be easily integrated into a silicon integrated circuit.
These objects are achieved by providing a BPSK encoder comprising a first circuit which processes a carrier signal and a binary signal to be encoded, and produces an output binary signal having synchronous phase shifts representing a change in the value of the signal to be encoded. Also, the first circuit is provided with a sampling signal from a second circuit. The second circuit comprises a delay circuit to deliver a shifted carrier signal that is smaller than the half-period of the carrier signal, and a logic gate for the logic combination of the carrier signal and the shifted carrier signal. The logic gate also delivers a binary sampling signal comprising at least two leading or trailing edges at each period of the carrier signal.
According to one embodiment, the first circuit can sample the signal to be encoded at the rate of the leading edges or at the rate of the trailing edges of the shifted carrier signal, and deliver a synchronized signal to be encoded. Additionally, the first circuit can deliver a composite signal equal to the shifted carrier signal or to the inverted shifted carrier signal depending on the logic value of the synchronized signal to be encoded. The first circuit can sample the composite carrier signal at the rate of the leading edges or at the rate of the trailing edges of the sampling signal, and deliver the output binary signal. The delay circuit may comprise at least two series-connected inverter gates.
Furthermore, the logic gate for producing the sampling signal may comprise an XOR gate which receives, at a first input, the carrier signal and, at a second input, the inverted shifted carrier signal. Also, the synchronized signal to be encoded may be delivered by a D type flip-flop circuit which receives the carrier signal at its clock input and the signal to be encoded at its D type input.
Additionally, the composite signal may be delivered by an XOR gate which receives, at a first input, the shifted carrier signal and, at a second input, the synchronized signal to be encoded. Moreover, the composite carrier signal may be sampled by a D type flip-flop circuit which receives the sampling signal at its clock input and the composite carrier signal at its D type input.
The present invention also relates to an integrated circuit with contactless operation, comprising an antenna coil and a switch to modulate the load of the antenna coil. The switch is driven by the output of an encoder according to the invention and as set forth above. The present invention also relates to a portable electronic device comprising such an integrated circuit.


REFERENCES:
patent: 4417219 (1983-11-01), Brossard et al.
patent: 4809296 (1989-02-01), Braun et al.
patent: 5153583 (1992-10-01), Murdoch
patent: 0 719 014 (1996-06-01), None
patent: 0 706 151 (1996-12-01), None
patent: 0 853 291 (1998-07-01), None
Patent Abstracts of Japan, vol. 098, No. 005, Apr. 30, 1998, and JP 10 013312 A (Sony Corp), Jan. 16, 1998.

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