Abrading – Precision device or process - or with condition responsive... – Computer controlled
Reexamination Certificate
2001-02-15
2004-03-30
Nguyen, Dung Van (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
Computer controlled
C451S008000
Reexamination Certificate
active
06712669
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of successfully modeling different end-point mode functions in order to maintain a constant and stable end-point detection curve for Chemical Mechanical Polishing (CMP).
(2) Description of the Prior Art
Inter-linear device distances have, over the years, become increasingly short due to the continued emphasis on semiconductor device performance improvements and device miniaturization. Semiconductor technological has evolved from Large Scale Integrated (LSI) devices to Very Large Scale Integration (VLSI) devices and ultimately to Ultra Large Scale Integration (ULSI) devices.
Photolithography is one of the predominant technologies that is used for the creation of semiconductor devices, photolithography advances are aimed at the creation of increasingly shallower focal depths that are needed for the creation of images in target surfaces. Due to the increasingly shallower focal depth, increased planarity of the target surfaces must be achieved. The reason for this is that a large step in a semiconductor surface, that is an abrupt change in the planarity of the surface, can have a severely negative impact on step coverage for the surface. If the gradation of the surface is too severe, poor deposition of for instance an overlying layer of metal can result, making it difficult to achieve a reliable semiconductor device. Further increases in semiconductor device density have frequently been achieved by implementing multi-layered configurations. This places further demands on the planarity of the surface over which overlying semiconductor device features are created. Optimum surface planarity has in recent years been obtained by applying methods of Chemical Mechanical Polishing (CMP) whereby semiconductor surfaces such as semiconductor substrates are uniformly polished to a high degree of planarity. The process is used to not only planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, but is also used for the removal of high elevation features, which are created during the fabrication of the microelectronic circuitry on the substrate.
A brief overview will be given at this time of the CMP process. A CMP apparatus typically consists of a rotating polishing platen on the surface of which an abrasive polishing pad is mounted. A wafer is mounted on the surface of a second rotating part, the wafer carrier. The surface of the rotating wafer is the surface that is to be polished. The mounting of the wafer to the wafer carrier is frequently achieved by means of a clamp ring. The surface of the rotating wafer is brought in contact with the rotating polishing pad, a slurry is distributed over the surface of the rotating wafer. The chemical slurry, which frequently includes abrasive materials, is maintained on the polishing pad with the objective of modifying the polishing characteristics of the polishing pad, enhancing the polishing of the substrate.
The process of chemical mechanical polishing to planarize semiconductor substrates is not without problems. These problems are typically more pronounced where the process of CMP is used to remove high elevation features, which have been created during the fabrication of microelectronic circuitry on the surface of the substrate. One of the most serious problems that is experienced in using chemical mechanical polishing is the limited ability to predict or control the rate and uniformity at which material is removed from the surface that is being polished. CMP is therefore as yet a labor-intensive process, since surface thickness and uniformity must be frequently monitored during the process of CMP in order to prevent over-polishing or inconsistent polishing of the substrate surface.
Of special concern in this respect is the non-homogeneous replenishment of slurry on the surface of the substrate and the polishing pad. The slurry is primarily used to enhance the rate at which selected materials are removed from the substrate surface. Non-homogeneous replenishment of slurry on the surface that is being polished contributes to unpredictability and non-uniformity of the polishing rate of the CMP process. In view of the fact that a fixed volume of slurry, which is in contact with the surface that is being polished, reacts with materials on the surface that is being polished, this fixed volume of slurry becomes less reactive as the process of polishing proceeds. As a consequence, the polishing enhancing characteristics of the fixed volume of slurry are significantly reduced during polishing. To counter this problem, fresh slurry is continuously provided to the surface of the polishing pad.
This latter approach presents at least two problems. Because of the physical configuration of the polishing apparatus, introducing fresh slurry into the area of contact between the substrate and the polishing pad is difficult. Providing a fresh supply of slurry to all locations on the surface of the substrate is even more difficult. As a result, the uniformity and the overall rate of polishing are significantly affected as the slurry reacts with the surface of the substrate that is being polished.
FIG. 1
shows a Prior Art CMP apparatus. A polishing pad
12
is attached to a polishing table
16
, rotating in a direction indicated by arrow
20
at a rate in the order of 1 to 200 RPM. A wafer carrier
14
holds wafer
10
(face down) against a polishing pad
12
. Wafer
10
is held in place by applying a vacuum (not shown) to the backside of the wafer
10
. Wafer carrier
14
also rotates, indicated by arrow
19
, typically in the same direction as polishing table
16
, rotating at a rate of about 1 to 200 RPM. The wafer traverses a circular polishing path over the polishing pad
12
, due to the rotation of polishing table
16
. Force
18
can also be applied against wafer
10
in the downward vertical direction and press the wafer
10
against the polishing pad
12
during the process of polishing. Force
18
is typically between about 0 and 15 pounds per square inch, force
18
is applied by shaft
17
that is attached to the back of wafer carrier
14
. Slurry
13
is provided to the top of the polishing pad
12
, this further enhances the polishing action of polishing pad
12
.
The Prior Art method that is highlighted in
FIG. 1
encounters a number of problems and concerns. For instance, abrasive polishing particles are lodged in and held by the polishing pad. By using the polishing pad, the fibers of the polishing pad deteriorate, causing abrasive particle retention within the polishing pad to diminish, reducing the polishing characteristics of the polishing pad. Also, due to the pressure that is applied to the wafer, the contact between the polishing pad and the wafer is intense and does not allow for an even distribution of the polishing slurry across the surface that is being polished. In addition, the abrasive particles that essentially affect the polishing action are, during the polishing process, reduced in size, further affecting the polishing characteristics of the process.
FIGS. 2
a
and
2
b
give an example of the process of Chemical Mechanical Polishing (CMP). The example that is shown in
FIGS. 2
a
and
2
b
is purposely kept simple and can readily be expanded to more complex examples of CMP. For all of these examples, the polishing process is essentially as the example that is shown in
FIGS. 2
a
and
2
b
. Over a semiconductor surface
10
, for instance the surface of a silicon substrate, a layer
22
of for instance silicon nitride is deposited, patterned and etched, creating openings or trenches
21
through the layer
22
and into the underlying semiconductor surface. These trenches have been filled with an overlying layer
24
, for instance comprising silicon oxide. It is the objective to fill the trenches
21
that have been created in layer
22
and the underlying semiconductor surface with a material. To achieve this objective, it is clear from
FIG
Ackerman Stephen B.
Nguyen Dung Van
Saile George O.
Schnabel Douglas R.
Tawain Semiconductor Manufacturing Company
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