Boundary test scheme for an intelligent device

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G01R 3128

Patent

active

053771990

ABSTRACT:
A testing apparatus for testing connectivity to a circuit board of an integrated circuit chip disposed on the circuit board. The circuit board has signal transmission circuitry. The integrated circuit chip has pins coupled to the signal transmission circuitry. The pins are for receiving digital signals asserted external to the chip. Each digital signal has a binary value depending upon whether the signal is asserted or not. The testing apparatus tests connectivity of the pins. The testing apparatus has signal assertion and reception circuitry that is coupled to the signal transmission circuitry of the circuit board but is not disposed on the chip. Command sensing, pin state storage, general storage, algorithm execution and general data output circuitry are all disposed on the chip to be tested. The command sensing circuitry is for sensing external assertion of a test command by the signal assertion and reception circuitry. The test command causes the chip to enter a test mode. The pin state storage circuitry is coupled to the pins and stores the binary values associated with the signals asserted by the signal assertion and reception circuitry. The general storage circuitry is for storing general digital data. The algorithm execution circuitry executes a test algorithm if the chip has entered the test mode. The test algorithm retrieves the binary values stored in the pin state storage circuitry, converts the binary values to general digital data, and stores the general digital data in the general storage circuitry. The general digital data output circuitry provides the general digital data stored in the general storage circuitry as output from the chip to the signal assertion and reception circuitry after the test algorithm has executed.

REFERENCES:
patent: 5285153 (1994-02-01), Ahanin et al.
patent: 5341380 (1994-08-01), Shoda

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