Boundary scan test method and apparatus

Details Boundary scan test method and apparatus Boundary scan test method and apparatus

1996-08-15

1998-12-08

DeCady, Albert

Excavating

371 2232, G01R 3128

Patent

active

058482350

ABSTRACT:
A boundary scan analog signal test circuit for boundary scan testing of analog signals. The boundary scan analog signal test circuit provides for known upper and lower bound values at specified times for testing whether sample analog signals are within the specified lower and upper bound values. If the sample analog signals are not between the known upper and lower bound values, the boundary scan analog signal test circuit produces a result flag indicating a "not pass" for the device being tested. If the sample analog signal being tested is found to be within the known upper and lower bound values, then the circuit generates a result flag indicating that the device being tested has passed the test.

REFERENCES:
patent: 5066909 (1991-11-01), Firooz
patent: 5210527 (1993-05-01), Smith et al.
patent: 5282213 (1994-01-01), Leigh et al.
patent: 5285152 (1994-02-01), Hunter
"Writing Correct and Usable Specifications for Board Test: A Case Study", Barry A. Alcorn, IEEE International Test Conference, Meeting the Test of Time, Aug. 1989, pp. 773-786.

Affiliated with

Also associated with

Rating

Boundary scan test method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Boundary scan test method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Boundary scan test method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-187646